Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors

Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors (1996)

by Kenneth M. Wilson , Kunle Olukotun , Mendel Rosenblum

Citations:

35 - 2 self

Datum	Value	Source
TITLE	Increasing Cache Port Efficiency for Dynamic Superscalar Microprocessors	INFERENCE
AUTHOR NAME	Kenneth M. Wilson	SVM HeaderParse 0.2
AUTHOR NAME	Kunle Olukotun	SVM HeaderParse 0.2
AUTHOR NAME	Mendel Rosenblum	SVM HeaderParse 0.2
ABSTRACT	The memory bandwidth demands of modern microprocessors require the use of a multi-ported cache to achieve peak performance. However, multi-ported caches are costly to implement. In this paper we propose techniques for improving the bandwidth of a single cache port by using additional buffering in the processor, and by taking maximum advantage of a wider cache port. We evaluate these techniques using realistic applications that include the operating system. Our techniques using a single-ported cache achieve 91 % of the performance of a dual-ported cache. 1.	SVM HeaderParse 0.2
YEAR	1996	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	147--157	INFERENCE
CITATIONS	35 found	ParsCit 1.0