A High-Performance Microarchitecture with Hardware-Programmable Functional Units

A High-Performance Microarchitecture with Hardware-Programmable Functional Units (1994)

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by Rahul Razdan , Michael D. Smith

Venue:	in Proceedings of the 27th Annual International Symposium on Microarchitecture
Citations:	171 - 1 self

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Datum	Value	Source
TITLE	A High-Performance Microarchitecture with Hardware-Programmable Functional Units	user correction - Legacy Corrections
AUTHOR NAME	Rahul Razdan	SVM HeaderParse 0.1
AUTHOR AFFIL	Harvard University, Cambridge	SVM HeaderParse 0.2
AUTHOR ADDR	MA 02138	SVM HeaderParse 0.1
AUTHOR NAME	Michael D. Smith	SVM HeaderParse 0.1
AUTHOR AFFIL	Harvard University, Cambridge	SVM HeaderParse 0.2
AUTHOR ADDR	MA 02138	SVM HeaderParse 0.1
ABSTRACT	This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC---a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language co...	user correction - Legacy Corrections
YEAR	1994	INFERENCE
VENUE	in Proceedings of the 27th Annual International Symposium on Microarchitecture	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	172--180	INFERENCE
CITATIONS	31 found	ParsCit 1.0