Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology

Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology (1997)

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by Lieven Vandenberghe , Stephen Boyd , Abbas El Gamal

Venue:	in Proc. Int. Conf. on Computer Aided Design
Citations:	22 - 7 self

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Datum	Value	Source
TITLE	Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology	user correction - Legacy Corrections
AUTHOR NAME	Lieven Vandenberghe	SVM HeaderParse 0.1
AUTHOR AFFIL	Electrical Engineering Dept.; University of California	SVM HeaderParse 0.2
AUTHOR ADDR	Los Angeles, CA 90095-1594	SVM HeaderParse 0.1
AUTHOR NAME	Stephen Boyd	SVM HeaderParse 0.1
AUTHOR AFFIL	2; Information Systems Laboratory; Electrical Engineering Dept.; Stanford University	SVM HeaderParse 0.2
AUTHOR ADDR	Stanford, CA 94305-9510	SVM HeaderParse 0.1
AUTHOR NAME	Abbas El Gamal	SVM HeaderParse 0.1
AUTHOR AFFIL	Information Systems Laboratory; Electrical Engineering Dept.; Stanford University	SVM HeaderParse 0.2
AUTHOR ADDR	Stanford, CA 94305-9510	SVM HeaderParse 0.1
ABSTRACT	Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and the Elmore delay as a measure of signal delay. If the RC circuit has a tree topology the sizing problem reduces to a convex optimization problem which can be solved using geometric programming. The tree topology restriction precludes the use of these methods in several sizing problems of significant importance to high-performance deep submicron design including, for example, circuits with loops of resistors, e.g., clock distribution meshes, and circuits with coupling capacitors, e.g., buses with crosstalk between the lines. The paper proposes a new optimization method which can be used to address these problems. The method uses the dominant time constant as a measure of signal propagation delay in an RC circuit, instead of Elmore delay. Using this measure, sizing of any RC circuit can be cast as a convex optimization problem which can be solved using the recently developed efficient interi...	user correction - Legacy Corrections
YEAR	1997	INFERENCE
VENUE	in Proc. Int. Conf. on Computer Aided Design	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	252--259	INFERENCE
CITATIONS	23 found	ParsCit 1.0