Performance-Driven Interconnect Design Based on Distributed RC Delay Model

Performance-Driven Interconnect Design Based on Distributed RC Delay Model (1993)

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by Jason Cong , Kwok-shing Leung , Dian Zhou

Venue:	in Proc. Design Automation Conf
Citations:	62 - 22 self

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Datum	Value	Source
TITLE	Performance-Driven Interconnect Design Based on Distributed RC Delay Model	user correction - Legacy Corrections
AUTHOR NAME	Jason Cong	SVM HeaderParse 0.1
AUTHOR AFFIL	Department of Computer Science Department of Electrical Engineering; University of California, Los Angeles University of North Carolina	SVM HeaderParse 0.2
AUTHOR ADDR	Los Angeles, CA 90024 Charlotte, NC 28213	SVM HeaderParse 0.1
AUTHOR NAME	Kwok-shing Leung	SVM HeaderParse 0.1
AUTHOR AFFIL	Department of Computer Science Department of Electrical Engineering; University of California, Los Angeles University of North Carolina	SVM HeaderParse 0.2
AUTHOR ADDR	Los Angeles, CA 90024 Charlotte, NC 28213	SVM HeaderParse 0.1
AUTHOR NAME	Dian Zhou	SVM HeaderParse 0.1
AUTHOR AFFIL	Department of Computer Science Department of Electrical Engineering; University of California, Los Angeles University of North Carolina	SVM HeaderParse 0.2
AUTHOR ADDR	Los Angeles, CA 90024 Charlotte, NC 28213	SVM HeaderParse 0.1
ABSTRACT	In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or near-optimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for high-performance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, ...	user correction - Legacy Corrections
YEAR	1993	INFERENCE
VENUE	in Proc. Design Automation Conf	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	606--611	INFERENCE
CITATIONS	16 found	ParsCit 1.0