Two Level Performance Estimator for High Level Synthesis of Analog Integrated Circuits with Feedback

Two Level Performance Estimator for High Level Synthesis of Analog Integrated Circuits with Feedback

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by Adrián Nuñez-Aldana , Ranga Vemuri

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Datum	Value	Source
TITLE	Two Level Performance Estimator for High Level Synthesis of Analog Integrated Circuits with Feedback	SVM HeaderParse 0.1
AUTHOR NAME	Adrián Nuñez-Aldana	user correction - Legacy Corrections
AUTHOR NAME	Ranga Vemuri	user correction - Legacy Corrections
AUTHOR AFFIL	Digital Design Environments Laboratory; Department of ECECS, University of Cincinnati	user correction - Legacy Corrections
AUTHOR ADDR	Cincinnati, OH 45221--0030	user correction - Legacy Corrections
ABSTRACT	In this paper, we present a technique for estimating the gain, bandwidth, power and area of analog integrated circuits. A two-step approach is adopted to speed up the estimation process and handle larger analog systems. In the first step, the performance of basic analog components is estimated using a knowledge-based approach. Then, component models are generated with the estimates produced at this phase. In the second phase, we use a symbolic analysis methodology to evaluate the performance at the system level. The system net-list is represented by a signal flow graph (SFG) using the component models generated at the previous phase. The SFG approach allows to handle feedback loops at the system level. 1 Introduction The analog synthesis process consists of two phases: topology selection and circuit sizing [1]. During the topology selection process, a net-list of components selected from a pre-defined library is generated. The generated topology should meet the specification requirem...	user correction - Legacy Corrections
CITATIONS	16 found	ParsCit 1.0