We describe an implementation of the PowerPC architecture using dynamic compilation techniques to an optimized VLIW target architecture called BOA. BOA is a variable length VLIW architecture with priority given not to minimizing cycles per instruction (CPI) but to maximizing processor frequency. By limiting the size of individual processor cores, multiples of them can be placed on a single die for SMP-on-a-chip configurations. BOA's dynamic optimization offers significant advantages over purely static compilation approaches like those Intel and Hewlett-Packard currently propose for the IA-64 architecture. Reliance on purely static profiling makes it impossible to adapt to changes in program usage. In addition, static profiling requires that independent software vendors (ISVs) perform extensive profiling and generate different executables optimized for a particular processor generation. Thus, the use of dynamic optimization enables two goals, (1) achieving efficient adaptation to specific workload behavior, and (2) optimizing for a specific implementation of the target platform.