Optimizing dominant time constant in RC circuits

Optimizing dominant time constant in RC circuits (1996)

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by Lieven Vandenberghe , Stephen Boyd , Abbas El Gamal

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Datum	Value	Source
TITLE	Optimizing dominant time constant in RC circuits	SVM HeaderParse 0.1
AUTHOR NAME	Lieven Vandenberghe	user correction - Legacy Corrections
AUTHOR NAME	Lieven V	user correction - Legacy Corrections
AUTHOR AFFIL	Information Systems Laboratory; Electrical Engineering Department; Stanford University	user correction - Legacy Corrections
AUTHOR ADDR	Stanford CA 94305	user correction - Legacy Corrections
AUTHOR NAME	Stephen Boyd	user correction - Legacy Corrections
AUTHOR AFFIL	Information Systems Laboratory; Electrical Engineering Department; Stanford University	user correction - Legacy Corrections
AUTHOR ADDR	Stanford CA 94305	user correction - Legacy Corrections
AUTHOR NAME	Abbas El Gamal	user correction - Legacy Corrections
AUTHOR AFFIL	Information Systems Laboratory; Electrical Engineering Department; Stanford University	user correction - Legacy Corrections
AUTHOR ADDR	Stanford CA 94305	user correction - Legacy Corrections
ABSTRACT	We propose to use the dominant time constant of a resistor-capacitor (RC) circuit as a measure of the signal propagation delay through the circuit. We show that the dominant time constant is a quasiconvex function of the conductances and capacitances, and use this property to cast several interesting design problems as convex optimization problems, specifically, semidefinite programs (SDPs). For example, assuming that the conductances and capacitances are affine functions of the design parameters (which is a common model in transistor or interconnect wire sizing), one can minimize the power consumption or the area subject to an upper bound on the dominant time constant, or compute the optimal tradeoff surface between power, dominant time constant, and area. We will also note that, to a certain extent, convex optimization can be used to design the topology of the interconnect wires. This approach has two advantages over methods based on Elmore delay optimization. First, it handles a far wider class of circuits, e.g., those with non-grounded capacitors. Second, it always results in convex optimization problems for which very efficient interiorpoint methods have recently been developed. We illustrate the method, and extensions, with several examples involving optimal wire and transistor sizing.	user correction - Legacy Corrections
YEAR	1996	user correction - Legacy Corrections
CITATIONS	38 found	ParsCit 1.0