Register File Design Considerations in Dynamically Scheduled Processors

Register File Design Considerations in Dynamically Scheduled Processors (1995)

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by Keith I. Farkas , Norman P. Jouppi , Paul Chow

Venue:	In Proceedings of the Second IEEE Symposium on High-Performance Computer Architecture
Citations:	40 - 1 self

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Datum	Value	Source
TITLE	Register File Design Considerations in Dynamically Scheduled Processors	user correction - Legacy Corrections
AUTHOR NAME	Keith I. Farkas	user correction - Legacy Corrections
AUTHOR AFFIL	d i g i t a l	user correction - Legacy Corrections
AUTHOR ADDR	Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA	user correction - Legacy Corrections
AUTHOR NAME	Norman P. Jouppi	user correction - Legacy Corrections
AUTHOR NAME	Paul Chow	user correction - Legacy Corrections
AUTHOR AFFIL	Lab (NSL) and the Systems Research Center (SRC). Another Digital research group is	user correction - Legacy Corrections
AUTHOR ADDR	located in Cambridge, Massachusetts (CRL).	user correction - Legacy Corrections
ABSTRACT	We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at processors capable of issuing either four or eight instructions per cycle and found that in most cases implementing precise exceptions requires a relatively small number of additional registers compared to imprecise exceptions. Systems with aggressive non-blocking load support were able to achieve performance similar to processors with perfect memory systems at the cost of some additional registers. Given our machine assumptions, we found that the performance of a four-issue machine with a 32-entry dispatch queue tends to saturate around 80 registers. For an eight-issue machine with a 64-entry dispatch queue performance does not saturate until about 128 registers. Assuming the machine cycle time is proportional to the register file cycle time, the 8-issue machine yields only 20% higher performance than the 4-issue machine due in part...	user correction - Legacy Corrections
YEAR	1995	user correction - Legacy Corrections
VENUE	In Proceedings of the Second IEEE Symposium on High-Performance Computer Architecture	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	40--51	INFERENCE
CITATIONS	77 found	ParsCit 1.0