Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search

Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (2001)

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by Frank Schenkel , Michael Pronath , Stephan Zizala , Robert Schwencker , Helmut Graeb , Kurt Antreich

Venue:	IEEE DAC
Citations:	14 - 1 self

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Datum	Value	Source
TITLE	Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search	user correction - Legacy Corrections
AUTHOR NAME	Frank Schenkel	user correction
AUTHOR AFFIL	1 Institute for Electronic Design Automation, Technical University of Munich	user correction
AUTHOR ADDR	80290 Munich, Germany; 2 Infineon Technologies AG, 81609 Munich, Germany	user correction
AUTHOR NAME	Michael Pronath	user correction
AUTHOR AFFIL	1 Institute for Electronic Design Automation, Technical University of Munich	user correction
AUTHOR ADDR	80290 Munich, Germany; 2 Infineon Technologies AG, 81609 Munich, Germany	user correction
AUTHOR NAME	Stephan Zizala	user correction
AUTHOR AFFIL	1 Institute for Electronic Design Automation, Technical University of Munich	user correction
AUTHOR ADDR	80290 Munich, Germany; 2 Infineon Technologies AG, 81609 Munich, Germany	user correction
AUTHOR NAME	Robert Schwencker	user correction
AUTHOR AFFIL	1 Institute for Electronic Design Automation, Technical University of Munich	user correction
AUTHOR ADDR	80290 Munich, Germany; 2 Infineon Technologies AG, 81609 Munich, Germany	user correction
AUTHOR NAME	Helmut Graeb	user correction
AUTHOR NAME	Kurt Antreich	user correction
AUTHOR AFFIL	1 Institute for Electronic Design Automation, Technical University of Munich	user correction
AUTHOR ADDR	80290 Munich, Germany; 2 Infineon Technologies AG, 81609 Munich, Germany	user correction
ABSTRACT	We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed methods were successfully applied to two example circuits for an industrial fabrication process.	user correction - Legacy Corrections
YEAR	2001	INFERENCE
VENUE	IEEE DAC	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	858--863	INFERENCE
CITATIONS	17 found	ParsCit 1.0