Efficient sorting using registers and caches

Efficient sorting using registers and caches (2000)

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by Rajiv Wickremesinghe , Lars Arge , Jeff Chase , Jeffrey Scott Vitter

Venue:	WAE, WORKSHOP ON ALGORITHM ENGINEERING , LECTURE NOTES IN COMPUTER SCIENCE
Citations:	7 - 0 self

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Datum	Value	Source
TITLE	Efficient sorting using registers and caches	user correction
AUTHOR NAME	Rajiv Wickremesinghe	user correction
AUTHOR AFFIL	Duke University	user correction
AUTHOR NAME	Lars Arge	user correction
AUTHOR AFFIL	Duke University	user correction
AUTHOR NAME	Jeff Chase	user correction
AUTHOR AFFIL	Duke University	user correction
AUTHOR NAME	Jeffrey Scott Vitter	user correction
AUTHOR AFFIL	Duke University	user correction
ABSTRACT	Modern computer systems have increasingly complex memory systems. Common machine models for algorithm analysis do not reflect many of the features of these systems, e.g., large register sets, lockup-free caches, cache hierarchies, associativity, cache line fetching, and streaming behavior. Inadequate models lead to poor algorithmic choices and an incomplete understanding of algorithm behavior on real machines. A key step toward developing better models is to quantify the performance effects of features not reflected in the models. This paper explores the effect of memory system features on sorting performance. We introduce a new cache-conscious sorting algorithm, R-merge, which achieves better performance in practice over algorithms that are superior in the theoretical models. R-merge is designed to minimize memory stall cycles rather than cache misses by considering features common to many system designs.	user correction
YEAR	2000	INFERENCE
VENUE	WAE, WORKSHOP ON ALGORITHM ENGINEERING , LECTURE NOTES IN COMPUTER SCIENCE	user correction
VENUE TYPE	CONFERENCE	INFERENCE
CITATIONS	24 found	ParsCit 1.0