Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management

Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management (2002)

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by Mohamed Shalan , Vincent J. Mooney III

Venue:	PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN (CODES'02
Citations:	10 - 2 self

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Datum	Value	Source
TITLE	Hardware Support for Real-Time Embedded Multiprocessor System-on-a-Chip Memory Management	user correction
AUTHOR NAME	Mohamed Shalan	user correction
AUTHOR AFFIL	Georgia Institute of Technology; School of Electrical and Computer Engineering	user correction
AUTHOR ADDR	801 Atlantic Drive; Atlanta, GA 30332-0250	user correction
AUTHOR NAME	Vincent J. Mooney III	user correction
AUTHOR AFFIL	Georgia Institute of Technology; School of Electrical and Computer Engineering	user correction
AUTHOR ADDR	801 Atlantic Drive; Atlanta, GA 30332-0250	user correction
ABSTRACT	The aggressive evolution of the semiconductor industry -- smaller process geometries, higher densities, and greater chip complexity -- has provided design engineers the means to create complex, high-performance Systems-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge memory, all on the same chip. Dealing with the global onchip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for the upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme -- which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation -- we present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing Element). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time (for an example of a four processing element SoC, the dynamic memory allocation of the global onchip memory takes sixteen cycles per allocation/deallocation in the worst case). In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU. Our example shows a multiprocessor SoC that utilizes the SoCDMMU has 440% overall speedup of the application transition time over fully shared memory that does not utilize the SoCDMMU.	user correction
YEAR	2002	INFERENCE
VENUE	PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN (CODES'02	user correction
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	79--84	INFERENCE
TECH	Tech. Rep. GIT-CC-03-02	INFERENCE
CITATIONS	24 found	ParsCit 1.0