Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program (2003)

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by Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell

Venue:	in Proc. of 16th International Conference on VLSI Design
Citations:	18 - 10 self

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Datum	Value	Source
TITLE	Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program	INFERENCE
AUTHOR NAME	Tezaswi Raja	SVM HeaderParse 0.2
AUTHOR AFFIL	Rutgers University	SVM HeaderParse 0.2
AUTHOR ADDR	Dept. of ECE Agere Systems Rutgers University, Dept. of ECE; Piscataway, NJ 08854, USA Murray Hill, NJ 07974, USA Piscataway, NJ 08854, USA	SVM HeaderParse 0.2
AUTHOR NAME	Vishwani D. Agrawal	SVM HeaderParse 0.2
AUTHOR AFFIL	Rutgers University	SVM HeaderParse 0.2
AUTHOR ADDR	Dept. of ECE Agere Systems Rutgers University, Dept. of ECE; Piscataway, NJ 08854, USA Murray Hill, NJ 07974, USA Piscataway, NJ 08854, USA	SVM HeaderParse 0.2
AUTHOR NAME	Michael L. Bushnell	SVM HeaderParse 0.2
AUTHOR AFFIL	Rutgers University	SVM HeaderParse 0.2
AUTHOR ADDR	Dept. of ECE Agere Systems Rutgers University, Dept. of ECE; Piscataway, NJ 08854, USA Murray Hill, NJ 07974, USA Piscataway, NJ 08854, USA	SVM HeaderParse 0.2
ABSTRACT	In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469-gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4-bit ALU circuit for which the power consumption was obtained by a circuit-level simulator. 1.	SVM HeaderParse 0.2
YEAR	2003	INFERENCE
VENUE	in Proc. of 16th International Conference on VLSI Design	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	527--532	INFERENCE
VOLUME	2003	INFERENCE
CITATIONS	27 found	ParsCit 1.0