Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems

Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems (1998)

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by Rainer Leupers , Peter Marwedel

Venue:	In Design Automation for Embedded Systems
Citations:	41 - 4 self

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Datum	Value	Source
TITLE	Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems	INFERENCE
AUTHOR NAME	Rainer Leupers	SVM HeaderParse 0.2
AUTHOR AFFIL	University of Dortmund, Department of Computer Science 12	SVM HeaderParse 0.2
AUTHOR ADDR	44221 Dortmund, Germany	SVM HeaderParse 0.2
AUTHOR NAME	Peter Marwedel	SVM HeaderParse 0.2
AUTHOR AFFIL	University of Dortmund, Department of Computer Science 12	SVM HeaderParse 0.2
AUTHOR ADDR	44221 Dortmund, Germany	SVM HeaderParse 0.2
ABSTRACT	Abstract. Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insu cient, because they do not provide exibility with respect to di erent target processors and also su er from inferior code quality. While recent research on code generation for embedded processors has primarily focussed on code quality issues, in this contribution we emphasize the importance of retargetability, and we describe an approachtoachieve retargetability. We propose usage of uniform, external target processor models in code generation, which describe embedded processors by means of RT-level netlists. Such structural models incorporate more hardware details than purely behavioral models, thereby permitting a close link to hardware design tools and fast adaptation to di erent target processors. The MSSQ compiler, which is part of the MIMOLA hardware design system, operates on structural models. We describe input formats, central data structures, and code generation techniques in MSSQ. The compiler has been successfully retargeted to a number of real-life processors, which proves feasibility of our approach with respect to retargetability. We discuss capabilities and limitations of MSSQ, and identify possible areas of improvement.	SVM HeaderParse 0.2
YEAR	1998	INFERENCE
VENUE	In Design Automation for Embedded Systems	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	1--36	INFERENCE
VOLUME	3	INFERENCE
CITATIONS	67 found	ParsCit 1.0