Architecture and implementation of memory channel 2

Architecture and implementation of memory channel 2 (1997)

by Marco Fillo , Richard B. Gillett

Venue:	Digital Technical Journal
Citations:	18 - 0 self

Datum	Value	Source
TITLE	Architecture and implementation of memory channel 2	INFERENCE
AUTHOR NAME	Marco Fillo	SVM HeaderParse 0.2
AUTHOR NAME	Richard B. Gillett	SVM HeaderParse 0.2
ABSTRACT	The MEMORY CHANNEL network is a dedicated cluster interconnect that provides virtual shared memory among nodes by means of internodal address space mapping. The interconnect implements direct user-level messaging and guarantees strict message ordering under all conditions, including transmission errors. These characteristics allow industry-standard communication interfaces and parallel programming paradigms to achieve much higher efficiency than on conventional networks. This paper presents an overview of the MEMORY CHANNEL network architecture and describes DIGITAL‘s crossbarbased implementation of the second-generation MEMORY CHANNEL network, MEMORY CHANNEL 2. This network provides bisection bandwidths of 1,000 to 2,000 megabytes per second and a sustained process-to-process bandwidth of 88 megabytes per second. One-way, processto-process message latency is less than 2.2 microseconds.	SVM HeaderParse 0.2
YEAR	1997	INFERENCE
VENUE	Digital Technical Journal	INFERENCE
VENUE TYPE	JOURNAL	INFERENCE
VOLUME	9	INFERENCE
TECH	Technical report	INFERENCE
CITATIONS	26 found	ParsCit 1.0