Towards optimal multi-level tiling for stencil computations

Towards optimal multi-level tiling for stencil computations (2007)

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by Lakshminarayanan Renganarayana , Manjukumar Harthikote-matha , Rinku Dewri , Sanjay Rajopadhye

Venue:	21st IEEE International Parallel and Distributed Processing Symposium (IPDPS
Citations:	6 - 0 self

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Datum	Value	Source
TITLE	Towards optimal multi-level tiling for stencil computations	INFERENCE
AUTHOR NAME	Lakshminarayanan Renganarayana	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Computer Science, Colorado State University	SVM HeaderParse 0.2
AUTHOR ADDR	USA	SVM HeaderParse 0.2
AUTHOR NAME	Manjukumar Harthikote-matha	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Computer Science, Colorado State University	SVM HeaderParse 0.2
AUTHOR ADDR	USA	SVM HeaderParse 0.2
AUTHOR NAME	Rinku Dewri	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Computer Science, Colorado State University	SVM HeaderParse 0.2
AUTHOR ADDR	USA	SVM HeaderParse 0.2
AUTHOR NAME	Sanjay Rajopadhye	SVM HeaderParse 0.2
AUTHOR AFFIL	Department of Computer Science, Colorado State University	SVM HeaderParse 0.2
AUTHOR ADDR	USA	SVM HeaderParse 0.2
ABSTRACT	Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many tiling and parallelization strategies are applicable to a given stencil computation. The best strategy depends not only on the combination of the two techniques, but also on many parameters: tile and loop sizes in each dimension; computation-communication balance of the code; processor architecture; message startup costs; etc. The best choices can only be determined through design-space exploration, which is extremely tedious and error prone to do via exhaustive experimentation. We characterize the space of multi-level tilings and parallelizations for 2D/3D Gauss-Siedel stencil computation. A systematic exploration of a part of this space enabled us to derive a design which is up to a factor of two faster than the standard implementation. 1.	SVM HeaderParse 0.2
YEAR	2007	INFERENCE
VENUE	21st IEEE International Parallel and Distributed Processing Symposium (IPDPS	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
CITATIONS	31 found	ParsCit 1.0