Exploiting hardware performance counters with flow and context sensitive profiling

Exploiting hardware performance counters with flow and context sensitive profiling (1997)

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by Glenn Ammons , Thomas Ball , James R. Larus

Venue:	ACM Sigplan Notices
Citations:	189 - 9 self

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Datum	Value	Source
TITLE	Exploiting hardware performance counters with flow and context sensitive profiling	INFERENCE
AUTHOR NAME	Glenn Ammons	SVM HeaderParse 0.2
AUTHOR AFFIL	Dept. of Computer Sciences Bell Laboratories Dept. of Computer Sciences; University of Wisconsin-Madison Lucent Technologies University of Wisconsin-Madison	SVM HeaderParse 0.2
AUTHOR NAME	Thomas Ball	SVM HeaderParse 0.2
AUTHOR AFFIL	Dept. of Computer Sciences Bell Laboratories Dept. of Computer Sciences; University of Wisconsin-Madison Lucent Technologies University of Wisconsin-Madison	SVM HeaderParse 0.2
AUTHOR NAME	James R. Larus	SVM HeaderParse 0.2
AUTHOR AFFIL	Dept. of Computer Sciences Bell Laboratories Dept. of Computer Sciences; University of Wisconsin-Madison Lucent Technologies University of Wisconsin-Madison	SVM HeaderParse 0.2
ABSTRACT	A program pro le attributes run-time costs to portions of a program's execution. Most pro ling systems su er from two major de ciencies: rst, they only apportion simple metrics, such as execution frequency or elapsed time to static, syntactic units, such as procedures or statements; second, they aggressively reduce the volume of information collected and reported, although aggregation can hide striking di erences in program behavior. This paper addresses both concerns by exploiting the hardware counters available in most modern processors and by incorporating two concepts from data ow analysis { ow and context sensitivity{to report more context for measurements. This paper extends our previous work on e cient path pro ling to ow sensitive pro ling, which associates hardware performance metrics with a path through a procedure. In addition, it describes a data structure, the calling context tree, that e ciently captures calling contexts for procedure-level measurements. Our measurements show that the SPEC95 benchmarks execute a small number (3{28) of hot paths that account for 9{98 % of their L1 data cache misses. Moreover, these hot paths are concentrated in a few routines, which have complex dynamic behavior. 1	SVM HeaderParse 0.2
YEAR	1997	INFERENCE
VENUE	ACM Sigplan Notices	INFERENCE
VENUE TYPE	CONFERENCE	INFERENCE
PAGES	85--96	INFERENCE
VOLUME	32	INFERENCE
CITATIONS	21 found	ParsCit 1.0