Abstract

Abstract-A memory hierarchy has coherence problems as soon--contents of the main memory--is copied in the-cache. One as one of its levels is split in several independent units-which are not says that such a datum-is present in the cache. If a processor p^|ilarl ad-onauMla frnw factor lnwale nr nrd%d%1Qlrc 'MA ' dIgQ;lea _ _.equaiiy auivieirU m iUster ieveIs Ur p1csws ine ciRss.141 solution to these problems, as found for instance in multiprocessor, multicache systems, is to restore a degree of interdependence between such units through a set of high speed interconnecting buses. ITis solution is not entirely satisfactory, as it tends to reduce the throughput of the memory hierarchy-and to increase its-cost. A new solution is presented and discussed here: the presence flag solution. It has both a lower cost and a lower overhead than the classical solution. A very important feature ofthis solution is that it is possible, in a cache-main memory subsystem, to delay updating the main memory until a block is needed in the cache (nonstore-through mode of operation). Index Terms-Caches, coherence, memory hierarchy, multi-processor systems, nonstore-through. I.