Abstract

Historically, there have been two methods for assessing microarchitectural ideas. Most groups use cycle-by-cycle simulation in software, but a few prefer to build hardware prototypes. The inexorable increase in scale and complexity of new architectural features is making both methods more difficult. Simulations are increasingly difficult to verify, and prototypes are growing costly and more time-consuming to build. This paper discusses our preliminary ideas on a middle ground between these two methodologies: using FPGA-based infrastructure for architecture research. The goal of such an approach is to reduce the conceptual distance between technological constraints and software simulation, but without the costs of a full-custom prototype. Our research group is designing and building the Bathysphere, a large-scale future-generation silicon emulation system from FPGA components. In this preliminary status report, we consider some of the aspects of traditional software simulation that might be complemented by emulation in FPGAs, as well as some of the modeling differences that remain when FPGAs are used instead of ASICs or full-custom ICs. We also present some preliminary data that highlights one of the many challenges in extracting meaningful data from an FPGA-based implementation: properly emulating multi-ported memory structures. 1

Citations