## Optimization objectives and models of variation for statistical gate sizing (2005)

Venue: | in GLSVLSI |

Citations: | 3 - 1 self |

### BibTeX

@INPROCEEDINGS{Guthaus05optimizationobjectives,

author = {Matthew R. Guthaus and Natesan Venkateswaran and Dennis Sylvester},

title = {Optimization objectives and models of variation for statistical gate sizing},

booktitle = {in GLSVLSI},

year = {2005},

pages = {312--316}

}

### OpenURL

### Abstract

This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exclusively on the optimization algorithms without considering the effects of the variation models and objective functions. This work empirically derives a simple variation model that is then used to optimize for robustness. Optimal results from example circuits used to study the effect of the statistical objective function on parametric yield.

### Citations

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(Show Context)
Citation Context ...mization is the representation of variation in timing models. Each physical parameter has a nominal value and some distribution which is most commonly assumed to be an independent Gaussian. Reference =-=[8]-=- is the seminal work that describes models for matching general properties of transistors. It is mostly concerned with intra-die (within-die) variation. The conclusion is that variability of certain p... |

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Citation Context ...eparate correlated random variables (Xi). For example, to model intra-die variation, there may be a correlated random variable for each region of a chip as described in [1] or by performing PCA as in =-=[4]-=-. A model for the delay variation coefficients, di, of the previous canonical delay model are now experimentally derived using Spice and a 180nm, 1.8V process. The variability parameters are shown in ... |

187 |
TILOS: A posynomial programming approach to transistor sizing
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Citation Context ...ives were used in the implementation of a statistical sizing tool that optimizes performance given a yield constraint of 3σ. The algorithm is a sensitivity-based sizing algorithm similar to reference =-=[5]-=-, but uses the µ − 3σ slack for all sensitivity calculations. Statistical timing is performed in an incremental, block-based manner as in reference [11]. This experiment uses three correlated paramete... |

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Citation Context ...lified delay model and a non-linear solver are used to remove any error due to heuristics in the optimization algorithm. Circuits are modeled using a gain-based delay model for the nominal delay (d0) =-=[10]-=-. Therefore, our nominal gate delay model is d0 = gh + p where h is the electrical effort (Cout/Cin), g is the logical effort, and p is the parasitic delay. The corresponding delay variation model is ... |

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Citation Context ...esign, moving to the next process technology will not provide the expected performance improvement. Recent developments in static statistical timing analysis (SSTA) have started to address this issue =-=[2, 11]-=-. All of these SSTA algorithms provide estimates of parametric yield which is defined as the number of chips that meet performance requirements over the total number of functional chips. Since SSTA pr... |

121 | Statistical timing analysis for intra-die process variations with spatial correlations
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(Show Context)
Citation Context ...component (dr) or by creating separate correlated random variables (Xi). For example, to model intra-die variation, there may be a correlated random variable for each region of a chip as described in =-=[1]-=- or by performing PCA as in [4]. A model for the delay variation coefficients, di, of the previous canonical delay model are now experimentally derived using Spice and a 180nm, 1.8V process. The varia... |

53 |
Statistical timing analysis using bounds and selective enumeration
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(Show Context)
Citation Context ...esign, moving to the next process technology will not provide the expected performance improvement. Recent developments in static statistical timing analysis (SSTA) have started to address this issue =-=[2, 11]-=-. All of these SSTA algorithms provide estimates of parametric yield which is defined as the number of chips that meet performance requirements over the total number of functional chips. Since SSTA pr... |

22 | Statistical optimization of leakage power considering process variations using dual-vth and sizing
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Citation Context ...593-057-4/05/0004 ...$5.00. Richard B. Brown University of Utah Salt Lake City, UT brown@coe.utah.edu Vladimir Zolotov IBM T.J. Watson Yorktown Heights, NY zolotov@us.ibm.com statistical optimization =-=[3, 9]-=-. Most of the work to date has focused on the optimization algorithm itself, ignoring the other factors such as the gate delay variability model, correlation, and the optimization objectives. These fa... |

21 | Uncertainty-aware circuit optimization
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Citation Context ...593-057-4/05/0004 ...$5.00. Richard B. Brown University of Utah Salt Lake City, UT brown@coe.utah.edu Vladimir Zolotov IBM T.J. Watson Yorktown Heights, NY zolotov@us.ibm.com statistical optimization =-=[3, 9]-=-. Most of the work to date has focused on the optimization algorithm itself, ignoring the other factors such as the gate delay variability model, correlation, and the optimization objectives. These fa... |

12 | A statistical gatedelay model considering intra-gate variability
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(Show Context)
Citation Context ...uch of circuit delay variability is of the inter-die (die-to-die) type. Given the results presented in [8], many other works have assumed that delay variation decreases with the gate size. References =-=[6, 7]-=- propose an analytic transistor (and gate) delay model that is linear with respect to the parameters and then examine the intra- and inter-chip and intra-gate variability assumption. They assume that ... |

5 | A Statistical Gate Delay Model for Intra-chip and Inter-chip Variabilities
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- 2003
(Show Context)
Citation Context ...uch of circuit delay variability is of the inter-die (die-to-die) type. Given the results presented in [8], many other works have assumed that delay variation decreases with the gate size. References =-=[6, 7]-=- propose an analytic transistor (and gate) delay model that is linear with respect to the parameters and then examine the intra- and inter-chip and intra-gate variability assumption. They assume that ... |