## Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation (2005)

Venue: | In ICCAD |

Citations: | 21 - 2 self |

### BibTeX

@INPROCEEDINGS{Chopra05parametricyield,

author = {Kaviraj Chopra and Saumil Shah and Ashish Srivastava and David Blaauw and Dennis Sylvester},

title = {Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation},

booktitle = {In ICCAD},

year = {2005},

pages = {1023--1028}

}

### OpenURL

### Abstract

With the increased significance of leakage power and performance variability, the yield of a design is becoming constrained both by power and performance limits, thereby significantly complicating circuit optimization. In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. We then show how this gradient information can be effectively used by a non-linear optimizer to perform yield optimization. We consider both inter-die and intra-die variations with correlated and random components. The proposed approach is implemented and tested and we demonstrate up to 40 % yield improvement compared to a deterministically optimized circuit. 1.

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Citation Context ...ents [17] a zi E( Pleake ) a zi ( P ) E( e ) ⎛ ⎞ ⎛ a ⎜ ⎟ = ⎜ i = log log ⎝ E leak ⎠ ⎝ ( ) ( ) ( ( ) ( ) ( ) ⎟⎟ b zi c zi E P + ⎞ leake E Pleake b c zi E P + E P E e Using the expressions developed in =-=[13]-=-, the remaining two P can be expressed as coefficients in the expression for a leak 1 ⎛ a = ⎜ 0 log 2 ⎜ ⎝ a ⎡ ( ( ) ( ) ( ( ) ( ) ( ) ( ) ( ) ⎟⎟ b b 4 E P + ⎞ leak E Pleak b b 2 E P + E P + Var P + Va... |

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Citation Context ...cutset-source set (nodes within the dashed shape) for node 8 1 This neglects the impact of the change in the slope of the circuit. However, the approach for timing analysis using backward propagation =-=[24]-=- can be used to consider their impact within the same framework. 7 8 8 9 9 10 10sHowever, the AT for all edges that are in the fanout cone of the fanin-set of node n changes. However we are only inter... |