## An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization (1993)

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Venue: | IEEE Transactions on Computer-Aided Design |

Citations: | 95 - 20 self |

### BibTeX

@ARTICLE{Sapatnekar93anexact,

author = {Sachin S. Sapatnekar and Vasant B. Rao and Pravin M. Vaidya and Sung-mo Kang},

title = {An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization},

journal = {IEEE Transactions on Computer-Aided Design},

year = {1993},

volume = {12},

pages = {1621--1634}

}

### Years of Citing Articles

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### Abstract

this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area

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Citation Context ...ent that it fans out to. Feedback loops in the circuit (e.g. crosscoupled NAND gates), which manifest themselves as strongly connected components in this graph, are identi ed using Tarjan's algorithm =-=[22]-=-. 25sNext, each clock signal is traced from the primary inputs, proceeding from a component to each of the components that it fans out to, until the signal intersects either a feedback loop or a trans... |

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Linear and Nonlinear Programming
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Citation Context ...polytope is a box, its center is easy to nd. At each subsequent iteration, a constraint of the form c T z is added to the previous polytope whose center is found iteratively using the Newton's method =-=[19]-=- as follows. The initial point z 0 for the Newton's method is found by moving halfway to the closest boundary in the direction c. The initial point z 0 thus obtained is guaranteed to be in the interio... |

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Citation Context ...rve; the curve for an 8-inverter chain is seen to be nonsmooth too. Also, one should curb an instinctive tendency to compare these variations with the smooth exponential variations of Mead and Conway =-=[24]-=-, since the two problems are not the same. The Mead-Conway problem principally di ers from ours in the following respects: (a) The objective of their problem is to minimize the number of stages and th... |

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Citation Context ...ircuit delay 7sspeci cations reported in this paper, it is seen in Section V that the approximation is valid. Since nding the LRP is equivalent to the longest path problem in a graph which is NP-hard =-=[18]-=-, we have developed a heuristic to perform this task. This heuristic is exact for series-parallel graphs, such as CMOS complex gates, and can be outlined as follows. T = maximum weighted spanning tree... |

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TILOS: a posynomial programming approach to transistor sizing
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Citation Context ... representing the circuit under the simplifying assumption that the input signals at the gate nodes of transistors are step functions. Such an assumption ensures that the delay function is posynomial =-=[3]-=-, but is not realistic, since actual signals have nonzero rise or fall times. Hedenstierna and Jeppson [4] have developed a delay model for 2 (2)sCMOS inverters that creates an equivalent RC network f... |

123 |
A new algorithm for minimizing convex functions over convex sets
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Citation Context ...eforms with non-zero rise and fall times, and computes rise and fall delays separately. The details of the delay estimation algorithm are furnished in Section II. An e cient convex programming method =-=[16]-=- is used for global optimization over the parameter space of all transistor sizes in a combinational subcircuit. This algorithm is capable of handling large problem sizes without having to prune any v... |

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Citation Context ...ditional planes, p has not changed since the last calculation of C ,1 , all that needs to be done to get the new C ,1 is a set of rank-one updates. If a new plane has been added, a method outlined in =-=[21]-=- may be used to update C ,1 . The method involves a rank-one update and a few additional operations to incorporate the e ect of the newly-added plane. As before, one of two schemes may be used to calc... |

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Citation Context ... where the exponents ij 2 R and the coe cients j > 0. Such a function has the useful property that it can be mapped onto a convex function through an elementary variable transformation, (xi) =(e zi ) =-=[1]-=-. j nY i=1 In this paper, the delay of a circuit is de ned to be the maximum of the delays of all paths in the circuit. Hence, it can be formulated as the maximum of posynomial functions. This is mapp... |

40 |
Optimization-Based Transistor Sizing
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Citation Context ...stors that lie on the critical path are increased, in an attempt to meet the delay constraint by increasing the sizes of as few transistors as possible. A subsequent algorithm proposed by Shyu et al. =-=[7]-=- works in two phases. It uses TILOS to generate a rough initial solution in the rst phase. In the second phase, it converts the problem to a mathematical optimization problem in a smaller parameter sp... |

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Transistor Size Optimization in the Tailor Layout System
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Citation Context ...ively reduces the delay along the critical path; it di ers from TILOS in that it changes the size of more than one transistor in each iteration. The methods used by Cirit [9], Hedlund [10] and Marple =-=[11, 12]-=- formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS [14] and iCOACH [15], is to perform the transistor size optim... |

13 |
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Citation Context ...RC network for the inverter when the signals at the gate nodes of transistors have nonzero rise or fall times. This model is also posynomial, and has been adapted in the transistor sizing tool, MOGLO =-=[5]-=-. The most commonly used measure of the circuit area is given by an a ne function of transistor sizes [3,5{12]. While this measure is not very accurate, it has the advantage of being a posynomial func... |

11 | CMOS Circuit Speed and Bu er Optimization - Hedenstierna, Jeppson - 1987 |

10 |
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Citation Context ...Due to the unimodal property of convex functions over convex x ij i sets, any local minimum of (1) is also a global minimum. Most approaches model the delay of a CMOS gate as the Elmore time constant =-=[2]-=- of an equivalent RC network representing the circuit under the simplifying assumption that the input signals at the gate nodes of transistors are step functions. Such an assumption ensures that the d... |

10 |
iCoach: A Circuit Optimization Aid for CMOS High-Performance Circuits
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Citation Context ...y Cirit [9], Hedlund [10] and Marple [11, 12] formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS [14] and iCOACH =-=[15]-=-, is to perform the transistor size optimization as a two-step iterative process. The rst step is an outer loop in which a timing `budget', Ti, is assigned to each gate i, using a coarse simpli cation... |

8 |
Transistor sizing for cmos circuits
- Cirit
(Show Context)
Citation Context ...iDEAS [8], like TILOS, iteratively reduces the delay along the critical path; it di ers from TILOS in that it changes the size of more than one transistor in each iteration. The methods used by Cirit =-=[9]-=-, Hedlund [10] and Marple [11, 12] formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS [14] and iCOACH [15], is to... |

8 |
MOSIZ: A Two-Step Transistor Sizing Algorithm based on Optimal Timing Assignment Method for Multi-Stage Complex Gates
- Dai, Asada
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(Show Context)
Citation Context ...eration. The methods used by Cirit [9], Hedlund [10] and Marple [11, 12] formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ =-=[13]-=-, CATS [14] and iCOACH [15], is to perform the transistor size optimization as a two-step iterative process. The rst step is an outer loop in which a timing `budget', Ti, is assigned to each gate i, u... |

6 |
Experiments Using Automatic Physical Design Techniques for Optimizing Circuit Performance
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- 1989
(Show Context)
Citation Context ...,5{12]. While this measure is not very accurate, it has the advantage of being a posynomial function of the sizes of transistors in the circuit. Various methods have been used for optimization. TILOS =-=[3, 6]-=-, performs the task by iteratively identifying a critical delay path, and using a heuristic method to reduce the delay along this path. The iterative process stops when the critical path (i.e., the la... |

6 |
Performance Optimization of Digital VLSI Circuits
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(Show Context)
Citation Context ...ively reduces the delay along the critical path; it di ers from TILOS in that it changes the size of more than one transistor in each iteration. The methods used by Cirit [9], Hedlund [10] and Marple =-=[11, 12]-=- formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS [14] and iCOACH [15], is to perform the transistor size optim... |

4 |
Transistor sizing for large combinational digital CMOS circuits
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(Show Context)
Citation Context ...e methods used by Cirit [9], Hedlund [10] and Marple [11, 12] formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS =-=[14]-=- and iCOACH [15], is to perform the transistor size optimization as a two-step iterative process. The rst step is an outer loop in which a timing `budget', Ti, is assigned to each gate i, using a coar... |

3 |
iDEAS: A Delay Estimator and Transistor Sizing Tool for CMOS Circuits
- Sapatnekar, Rao
- 1990
(Show Context)
Citation Context ...tors on the paths of worst delay), and uses a method of feasible directions to nd the optimal solution. The use of the reduced space serves to reduce the complexity of the optimization problem. iDEAS =-=[8]-=-, like TILOS, iteratively reduces the delay along the critical path; it di ers from TILOS in that it changes the size of more than one transistor in each iteration. The methods used by Cirit [9], Hedl... |

1 |
AESOP :Atoolforautomated transistor sizing
- Hedlund
- 1987
(Show Context)
Citation Context ...ke TILOS, iteratively reduces the delay along the critical path; it di ers from TILOS in that it changes the size of more than one transistor in each iteration. The methods used by Cirit [9], Hedlund =-=[10]-=- and Marple [11, 12] formulate non-linear programs, and solve them by the method of Lagrangian multipliers. Another approach, as practised in MOSIZ [13], CATS [14] and iCOACH [15], is to perform the t... |

1 |
Private communication
- Fishburn
- 1992
(Show Context)
Citation Context ...0 MB 15.0ns 633.9 258.7s 89 y 3.1 MB 10.0ns 1125.8 429.4s 105 y 3.2 MB (y largest number of iterations required by a combinational subcircuit) In a comparison with the optimization algorithm of TILOS =-=[3, 6, 23]-=-, using the same delay models for both algorithms, it was found that when the delay speci cation was loose, the area of the TILOS-sized circuit was close (within a few tenths of a percent) to the 29so... |