An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization (1993)
| Venue: | IEEE Transactions on Computer-Aided Design |
| Citations: | 81 - 18 self |
BibTeX
@ARTICLE{Sapatnekar93anexact,
author = {Sachin S. Sapatnekar and Vasant B. Rao and Pravin M. Vaidya and Sung-mo Kang},
title = {An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization},
journal = {IEEE Transactions on Computer-Aided Design},
year = {1993},
volume = {12},
pages = {1621--1634}
}
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Abstract
this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area
