## Generation of yield-aware pareto surfaces for hierarchical circuit design space exploration (2006)

Venue: | In DAC |

Citations: | 9 - 0 self |

### BibTeX

@INPROCEEDINGS{Tiwary06generationof,

author = {Saurabh K Tiwary},

title = {Generation of yield-aware pareto surfaces for hierarchical circuit design space exploration},

booktitle = {In DAC},

year = {2006},

pages = {31--36}

}

### OpenURL

### Abstract

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.

### Citations

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(Show Context)
Citation Context ...ard circuit optimization techniques, are used to approximate the pareto surface. Another method often employed for generating these pareto fronts is the non-dominated sorting genetic algorithm (NSGA) =-=[7]-=-. The basic idea is to start with a population of samples in the parameter space. These sets of parameters for points in the parameter space (individuals) are called chromosomes. During each generatio... |

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Citation Context ...n the performance space of the circuits has often been used with these macromodeling tools for hierarchical synthesis of larger systems [13]. These pareto surfaces can be generated by both stochastic =-=[19]-=- [17] and deterministic algorithms [6] [15]. Pareto surfaces represent the best performance that can be obtained from a given circuit topology across its complete design space. These surfaces are gene... |

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Citation Context ... performance space of the circuits has often been used with these macromodeling tools for hierarchical synthesis of larger systems [13]. These pareto surfaces can be generated by both stochastic [19] =-=[17]-=- and deterministic algorithms [6] [15]. Pareto surfaces represent the best performance that can be obtained from a given circuit topology across its complete design space. These surfaces are generated... |

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Citation Context ...point (that we call anchor points) is generally very expensive since it requires evaluation of the performance function for large number of input process parameter sets. Latin Hypercube (LH) sampling =-=[4]-=- is the most common method to reduce the number of evaluations required while still ensuring reasonable accuracy in computing the performance distribution function. In our methodology, we generate set... |

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Citation Context ...ION Recent advances in design automation and increased computational power has led to a gradual transition from “hand-calculation” based analog circuit design to a simulation-based sizing methodology =-=[3]-=-. Simulation based synthesis uses efficient global optimization techniques to visit many circuit candidates, and fully evaluates each candidate via detailed simulation. This methodology works very wel... |

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Citation Context ... has often been used with these macromodeling tools for hierarchical synthesis of larger systems [13]. These pareto surfaces can be generated by both stochastic [19] [17] and deterministic algorithms =-=[6]-=- [15]. Pareto surfaces represent the best performance that can be obtained from a given circuit topology across its complete design space. These surfaces are generated for the nominal values of the pr... |

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Citation Context ...timal design points becomes too large for these circuits to be handled by the tools available today. To handle this problem, methods for modeling the performance space of circuits have been presented =-=[10]-=- [14] [5]. Using Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit ... |

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Citation Context ... be done for topology selection [9] as well as circuit synthesis[13]. Of late, much work has been done in the field of analog circuit macromodeling which aims at simulating these circuits faster [16] =-=[8]-=- [12]. These macromodels capture the important functional characteristics of the circuit while discarding the redundant information. They are faster to simulate than the original transistor level circ... |

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Citation Context ...s, obtained during Monte Carlo simulations of the circuit, to a Normal distribution using minimal number of parameters. The optimization is performed using Brent-Powell based local optimzation scheme =-=[18]-=-. The metric for resemblance is the sum of squared error between the distribution functions. j d y = a + b ∗ (x + c) (6) y = a + b ∗ log(c ∗ x + d) Once the optimal transformation is obtained, we pick... |

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Citation Context ... often been used with these macromodeling tools for hierarchical synthesis of larger systems [13]. These pareto surfaces can be generated by both stochastic [19] [17] and deterministic algorithms [6] =-=[15]-=-. Pareto surfaces represent the best performance that can be obtained from a given circuit topology across its complete design space. These surfaces are generated for the nominal values of the process... |

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Citation Context ...done for topology selection [9] as well as circuit synthesis[13]. Of late, much work has been done in the field of analog circuit macromodeling which aims at simulating these circuits faster [16] [8] =-=[12]-=-. These macromodels capture the important functional characteristics of the circuit while discarding the redundant information. They are faster to simulate than the original transistor level circuit a... |

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Citation Context ...ra.ac.in Rob A Rutenbar Carnegie Mellon University Pittsburgh,PA USA rutenbar@ece.cmu.edu these performance models, efficient system level design space explorations can be done for topology selection =-=[9]-=- as well as circuit synthesis[13]. Of late, much work has been done in the field of analog circuit macromodeling which aims at simulating these circuits faster [16] [8] [12]. These macromodels capture... |

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Citation Context ... Mellon University Pittsburgh,PA USA rutenbar@ece.cmu.edu these performance models, efficient system level design space explorations can be done for topology selection [9] as well as circuit synthesis=-=[13]-=-. Of late, much work has been done in the field of analog circuit macromodeling which aims at simulating these circuits faster [16] [8] [12]. These macromodels capture the important functional charact... |

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Citation Context ...s can be done for topology selection [9] as well as circuit synthesis[13]. Of late, much work has been done in the field of analog circuit macromodeling which aims at simulating these circuits faster =-=[16]-=- [8] [12]. These macromodels capture the important functional characteristics of the circuit while discarding the redundant information. They are faster to simulate than the original transistor level ... |