## CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation

### Cached

### Download Links

- [www.cecs.uci.edu]
- [www.cecs.uci.edu]
- [cobweb.ecn.purdue.edu]
- DBLP

### Other Repositories/Bibliography

Citations: | 12 - 0 self |

### BibTeX

@MISC{Ghosh_crista:a,

author = {Swaroop Ghosh and Swarup Bhunia and Kaushik Roy},

title = {CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation},

year = {}

}

### OpenURL

### Abstract

Abstract—Design considerations for robustness with respect to variations and low-power operations typically impose contradictory design requirements. Low-power design techniques such as voltage scaling, dual-Vth, etc., can have a large negative impact on parametric yield. In this paper, we propose a novel paradigm for low-power variation-tolerant circuit design called CRitical path ISolation for Timing Adaptiveness (CRISTA), which allows aggressive voltage scaling. The principal idea includes the following: 1) isolate and predict the set of possible paths that may become critical under process variations; 2) ensure that they are activated rarely; and 3) avoid possible delay failures in the critical paths by dynamically switching to two-cycle operation (assuming all standard operations are single cycle), when they are activated. This allows us to operate the circuit at reduced supply voltage while achieving the required yield. Simulation results on a set of benchmark circuits with Berkeley-predictive-technology-model [BPTM 70 nm: Berkeley predictive technology model] 70-nm devices that show an average of 60 % improvement in power with small overhead in performance and 18 % overhead in die area compared to conventional design. We also present two applications of the proposed methodology that include the following: 1) pipeline design for low power and 2) temperature-adaptive circuit design. Index Terms—Low power, process variation-tolerant design, supply voltage scaling, temperature-aware design.

### Citations

383 | Temperature-aware microarchitecture: Modeling and implementation - Skadron, Stan, et al. - 2004 |

218 | Razor: a low-power pipeline based on circuit-level timing speculation
- ERNST, KIM, et al.
- 2003
(Show Context)
Citation Context ...issipation. Researchers have investigated logic design approaches that are robust with respect to process variations and, at the same time, suitable for aggressive voltage scaling. One such technique =-=[3]-=- uses dynamic detection and correction of circuit timing errors to tune processor supply voltage. Design optimization techniques using gate sizing and dual-Vth assignment to improve power/area typical... |

183 |
Digital Integrated Circuits
- Rabaey
- 1998
(Show Context)
Citation Context ...ake of simplicity, we choose a 4-bit ripple carry adder as shown in Fig. 1. Signals P 0-P 3 (G 0-G 3) are the propagate (generate) signals whereas C i,0 (C o,1-C o,3) are carry-in (carry-out) signals =-=[5]-=-. As evident, the path from carry-in to carry-out is critical and determines the frequency of operation of the adder. However, note that the critical path is activated only when C i,0 = 1 and at the s... |

152 | Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management - Skadron, Abdelzaher, et al. |

50 | Power and temperature control on a 90-nm Itanium family processor - McGowen, Poirier, et al. - 2006 |

39 | Design and reliability challenges in nanometer technologies - Borkar, Karnik, et al. - 2004 |

36 | Novel Sizing Algorithm for Yield Improvement Under Process Variation in Nanometer Technology - Choi, Paul, et al. - 2004 |

22 | Statistical optimization of leakage power considering process variations using dual-Vth and sizing - Srivastava, Sylvester, et al. |

21 | Uncertainty-aware circuit optimization - Bai, Visweswariah, et al. - 2002 |

9 | SM’95–F’01) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology - Roy - 1990 |

7 | et al., “Statistical timing analysis using levelized covariance propagation - Kang |

6 |
et al. Statistical optimization of leakage power considering process variations using dual-vth and sizing
- Srivastava
- 2004
(Show Context)
Citation Context ...he past few years, statistical design approach has been widely investigated as an effective method to ensure yield under process variations. Several gate-level sizing and/or Vth assignment techniques =-=[1]-=- have been proposed recently addressing the minimization of total power while maintaining the timing yield. On the other end of the spectrum, design techniques (e.g., adaptive body biasing [2]) have b... |

5 |
et al., “Uncertainty-Aware Circuit Optimization
- Bai
- 2002
(Show Context)
Citation Context ...Design optimization techniques using gate sizing and dual-Vth assignment to improve power/area typically increase the number of critical paths in a circuit, giving rise to the so-called “wall effect” =-=[4]-=-. The uncertainty-aware design technique [4] describes an optimization process to reduce the wall effect. However, it does not address the problem of power dissipation. In this paper, we present a nov... |

4 | A novel synthesis approach for active leakage power reduction using dynamic supply gating - Bhunia, Banerjee, et al. - 2005 |

4 | was with the Semiconductor Process and Design - He - 1993 |

3 |
et al. Design and reliability challenges in nanometer technologies
- Borkar
- 2004
(Show Context)
Citation Context ...hniques [1] have been proposed recently addressing the minimization of total power while maintaining the timing yield. On the other end of the spectrum, design techniques (e.g., adaptive body biasing =-=[2]-=-) have been proposed for post-silicon process compensation and process adaptation to deal with process-related timing failures. Due to quadratic dependence of dynamic power of a circuit on its operati... |

3 |
et al., Timed Shannon Circuits: A
- Lavagno
- 1995
(Show Context)
Citation Context ...performing an input based partition of the circuit such that the critical paths are isolated and their activation probability is reduced. To achieve this, we used Shannon expansion based partitioning =-=[7]-=- which partitions a Boolean expression f into disjoint sub-expressions as shown below: f ( x ,..., x ,..., x ) = x. f ( x ,..., x = 1,..., x )+ x . f ( x ,..., x = 0,..., x ) 1 i n i 1 i n i 1 i n = x... |

3 |
et al., A Novel Synthesis Approach for Active Leakage Power Reduction Using Dynamic Supply Gating, DAC
- Bhunia
- 2005
(Show Context)
Citation Context .... CF + x x . CF + x x . CF + x x . CF (7) 1 i n i j 1 i j 2 i j 3 i j 4 Control variable selection plays a very important role in achieving desired goals in Shannon’s expansion based partitioning. In =-=[8, 9]-=-, the most binate variable is chosen as control variable to minimize the area overhead. However, this heuristic may not lead to the confinement of critical paths of the circuit after expansion. For ex... |

2 | expansion based supply-gated logic for improved power and testability - Ghosh, Bhunia, et al. |

2 | and the M.Tech. degree from the Indian Institute of Technology - University, Kolkata, et al. - 1995 |

2 |
et al., Novel sizing algorithm for yield improvement under process variation in nanometer
- Paul
- 2004
(Show Context)
Citation Context ...zing because in this case, the critical paths are made slower while non-critical paths are made faster. We follow the above mentioned sizing strategy in a Lagrangian Relaxation (LR) based gate sizing =-=[12]-=- as shown in Table 1. Given a delay target (Tc), it tries to meet the yield requirement with minimum area. The procedure takes gList (i.e., list of cofactors) and determines the cofactor at highest le... |

1 | 70 nm: Berkeley Predictive Technology Model. [Online]. Available: www.eas.asu.edu/~ptm [7 - BPTM - 1995 |

1 | 10] 2006Synopsys Design Compiler. (2006). [Online]. Available: www. synopsys.com [11 - Kang, Paul, et al. |

1 | received the B.E. degree (Hons.) in electrical engineering from Indian Institute of Technology, Roorkee, India, in 2000 and the M.S. degree from the University of - Ghosh - 2004 |

1 | 2000 to 2002, he was with Mindtree Technologies Pvt - From |

1 | received the 2005 SRC Technical Excellence Award as a team member, Best Paper Award - Bhunia - 2005 |

1 |
et al., Design of robustly testable combinational logic circuits
- Kundu
- 1991
(Show Context)
Citation Context .... CF + x x . CF + x x . CF + x x . CF (7) 1 i n i j 1 i j 2 i j 3 i j 4 Control variable selection plays a very important role in achieving desired goals in Shannon’s expansion based partitioning. In =-=[8, 9]-=-, the most binate variable is chosen as control variable to minimize the area overhead. However, this heuristic may not lead to the confinement of critical paths of the circuit after expansion. For ex... |