Abstract

research relevant to the design and application of high performance scientific computers. We test our ideas by designing, building, and using real systems. The systems we build are research prototypes; they are not intended to become products. There is a second research laboratory located in Palo Alto, the Systems Research Center (SRC). Other Digital research groups are located in Paris (PRL) and in Cambridge,

Citations

745	Improving direct-mapped cache performance by the addition of a small fullyassociative cache and prefetch buffers - Jouppi - 1990
677	A data locality optimizing algorithm - Wolf, Lam - 1991
587	Cache Memories - Smith - 1982
339	Limits of Instruction-Level Parallelism - Wall - 1991
249	HANSEN: Profile Guided Code Positioning - PETTIS, C - 1990
169	Global register allocation at link time - Wall - 1986
156	The effect of context switches on cache performance - Mogul, Borg - 1991
149	Aspects of Cache Memory and Instruction Buffer Performance - Hill - 1987
140	Predicting program behavior using real or estimated pro les - Wall - 1991
138	Program optimization for instruction caches - McFarling - 1989
136	Achieving high instruction cache performance with an optimizing compiler - Hwu, Chang - 1989
74	Long Address Traces from RISC Machines: Generation and Analysis - Borg, Kessler, et al. - 1989
68	Language as the Machine Description - Wall, Powell - 1987
62	A simulation based study of TLB performance - Chen, Borg, et al. - 1992
60	Simple and flexible datagram access controls for UNIX-based gateways - Mogul - 1989
59	Performance tradeoffs in cache design - Przybylski, Horowitz, et al. - 1988
57	Mostly-Copying garbage collection picks up generations and C - Bartlett - 1989
53	Experience with a Software-defined Machine Architecture - Wall - 1991
47	Visa Protocols for Controlling Inter-Organizational Datagram Flow: Extended Description." "Cache Coherence in Distributed Systems - Anand - 1987
47	WRL Research Report 88/5 - Bartlett - 1987
47	WRL Research Report 89/2 - Hamburgen - 1987
43	WRL Research Report 89/1 - Turrini - 1987
41	Michael ‘‘Measured Capacity of an Ethernet - Mogul, Rashid - 1987
38	Pool Boiling Enhancement Techniques for Water at Low Pressure - McGillis, Fitch, et al. - 1990
38	A 20-MIPS Sustained 32-bit CMOS Microproces"1990 DECWRL/Livermore Magic Release." sor with High Ratio of Sustained to Peak PerforRobert - Jouppi, Tang
36	Characteristics of Performance-Optimal Multi-Level Cache Hierarchies - Przybylski, Horowitz, et al. - 1989
36	Incremental, Generational Mostly-Copying Garbage Collection in Uncooperative Environ"A Smart Frame Buffer." ments - Yip - 1992
33	MTOOL: A Method For Detecting Memory Bottlenecks.’’ Aaron Goldberg and - Hennessy - 1990
32	Optimal Finned Heat Sinks." William R. Hamburgen. "Compacting Garbage Collection with Ambiguous WRL - Bartlett - 1986
32	Michael "Measured Capacity of an Ethernet - Mogul, Rashid - 1987
32	Fragmentation Considered Harmful." WRL Research Report 88/4 - Kent, Mogul - 1988
32	Pool Boiling on Small Heat Dissipating Elements in Water at Subatmospheric Pressure - McGillis, Fitch, et al. - 1992
32	Interleaved Fin Thermal Connectors for Multichip Modules - Hamburgen - 1991
32	Experience: Using an Intermediate WRL Research Report 88/2 - Mahler - 1988
29	DECWRL/Livermore Magic Release - Mayo, Arnold, et al. - 1990
26	Report 90/4 - Research - 1990
24	Compacting Garbage Collection with Ambiguous WRL - Hamburgen - 1986
24	Fragmentation Considered Harmful.’’ WRL Research Report 88/4 - Kent, Mogul - 1988
22	Noise Issues in the ECL Circuit Family." Jeffrey Y.F. Tang and - Yang - 1990
22	Vector/Scalar Floating-Point Architecture - Unified - 1989
21	Efficient Generation of Test Patterns Using Boolean Satisfiablilty." "Available Instruction-Level Parallelism for SuperTracy Larrabee. scalar and - Jouppi, Wall - 1990
16	A Unified Vector/Scalar Floating-Point Architecture. " "Virtual Memory vs. The File System - Wall - 1990
16	WRL Research Report 89/8 - Jouppi - 1990
16	WRL Research Report 89/9 - Jouppi - 1990
16	1990 DECWRL/Livermore Magic Release." "A 20-MIPS Sustained 32-bit CMOS MicroprocesRobert - Mayo, Arnold, et al. - 1990
15	Instuction Cache Replacement Policies and Organizations - Smith, Goodman - 1985
15	Reports "Titan System Manual." "MultiTitan: Four Architecture Papers - Research - 1986
15	Simple and Flexible Datagram Access Controls for "Link-Time Code Modification." Unix-based Gateways - Wall - 1987
15	Available Instruction-Level Parallelism for SuperWRL Research Report 90/2 - Larrabee - 1990
15	Writing Fast X Servers for Dumb Color Frame Buf- "Long Address Traces from RISC Machines: fers." Generation and Analysis - Wall - 1991