## Efficient decoupling capacitor planning via convex programming methods (2006)

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Venue: | Proc. Int. Symp. Phy |

Citations: | 1 - 0 self |

### BibTeX

@INPROCEEDINGS{Kahng06efficientdecoupling,

author = {Andrew B. Kahng},

title = {Efficient decoupling capacitor planning via convex programming methods},

booktitle = {Proc. Int. Symp. Phy},

year = {2006},

pages = {102--107}

}

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### Abstract

Achieving power/ground (P/G) supply signal integrity is crucial to success of nanometer VLSI designs. Existing P/G network optimization techniques are dominated by sensitivity based approaches. In this paper, we propose two novel convex programming based approaches for decoupling capacitor insertion in a P/G network, i.e., a semidefinite program and a linear program, which are global optimizations with theoretically guaranteed supply voltage degradation bounds. We also propose a scalability improvement scheme which enables us to apply the proposed convex programs to industry designs. We present a simple illustrative example and experimental results on an industry design, which show that the proposed semidefinite program guarantees supply voltage degradation bound for all possible supply current sources, while the proposed linear program achieves the most accurate supply voltage degradation control for a given set of supply current sources.

### Citations

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Citation Context ...new optimization technique, which finds applications in control systems engineering and relaxations of combinatorial optimization problems such as graph partitioning and quadratic assignment problems =-=[1, 6, 17]-=-. Boyd et al. propose a semidefinite program formulation for VLSI interconnect timing optimization as follows [16]. Minimize t Sub ject to tG −C � 0 (2) where scalar t is an upper bound of the delays ... |

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Citation Context ...new optimization technique, which finds applications in control systems engineering and relaxations of combinatorial optimization problems such as graph partitioning and quadratic assignment problems =-=[1, 6, 17]-=-. Boyd et al. propose a semidefinite program formulation for VLSI interconnect timing optimization as follows [16]. Minimize t Sub ject to tG −C � 0 (2) where scalar t is an upper bound of the delays ... |

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Citation Context ...nt on the package level, while on-chip inductance in today’s power supply networks usually do not affect analysis results [2, 9]. Frequency domain techniques, e.g., interconnect model order reduction =-=[10, 11]-=-, can be applied for P/G network analysis without significant loss of accuracy [13, 19], because an RC network acts as a low-pass filter, where node waveforms can be approximated closely by sinusoids ... |

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Citation Context ...nt on the package level, while on-chip inductance in today’s power supply networks usually do not affect analysis results [2, 9]. Frequency domain techniques, e.g., interconnect model order reduction =-=[10, 11]-=-, can be applied for P/G network analysis without significant loss of accuracy [13, 19], because an RC network acts as a low-pass filter, where node waveforms can be approximated closely by sinusoids ... |

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Citation Context ...rrent sources for the switching gates (Fig. 1). Inductance effect is significant on the package level, while on-chip inductance in today’s power supply networks usually do not affect analysis results =-=[2, 9]-=-. Frequency domain techniques, e.g., interconnect model order reduction [10, 11], can be applied for P/G network analysis without significant loss of accuracy [13, 19], because an RC network acts as a... |

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Citation Context ...tion [2]. Voltage “droop”, or, time domain supply voltage drop integral at all violation nodes, is given by adjoint sensitivity analysis, and is fed into a quadratic solver for nonlinear optimization =-=[14]-=-. Sensitivitybased optimization approaches require repeated transient simulation of a P/G network at each optimization step, which is quite time consuming. Further, the resultant problem is a general ... |

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Citation Context ...e bound into a timing bound, we consider delay from launch of step supply currents to the time that a node voltage reaches the αVdd voltage bound. Elmore delay upper bounds 50% delay in an RC network =-=[7]-=-, and is given by normalized M0 as follows. T elm = M0 = M−1 G−1CG−1Jˆ (8) G−1Jˆ We lower bounds a 50% delay in an RC network by k times Elmore delay, e.g., k = lg2, which is the 50% delay for a singl... |

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Citation Context ...lly do not affect analysis results [2, 9]. Frequency domain techniques, e.g., interconnect model order reduction [10, 11], can be applied for P/G network analysis without significant loss of accuracy =-=[13, 19]-=-, because an RC network acts as a low-pass filter, where node waveforms can be approximated closely by sinusoids [2]. Modified nodal analysis (MNA) in an interconnect is presented in [10]. For smaller... |

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Citation Context ...l linear constraints. On-chip inductance is negligible for most of designs in today’s technologies [2, 9]. For inductance effect in future technology, an equivalent Elmore delay for RLC interconnects =-=[8]-=- can be applied based on the first two orders of moments. However, there will be no theoretically guaranteed bound on delay or voltage in the presence of significant inductance effect. 3.4 An Illustra... |

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Citation Context ...ty analysis, e.g., small (large) change sensitivity is proposed as the voltage sensitivity of a node (all violation nodes) with respect to all decoupling capacitors, and enables a greedy optimization =-=[2]-=-. Voltage “droop”, or, time domain supply voltage drop integral at all violation nodes, is given by adjoint sensitivity analysis, and is fed into a quadratic solver for nonlinear optimization [14]. Se... |

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Citation Context ...(V ) by linear program (LP), semidefinite program (SDP), and θ heuristic for free nodes 2, 3 and 4 in Fig. 3. peak current (A) method decap (pF) delay (ns) vdrop (V ) LP [0,1.443,0] 1 0.5 [0,1,0] SDP =-=[3,4,3]-=- 3.65 0.2 θ [0,1,0] 0.703 0.628 LP [1.924,0,0] 1 0.5 [0.67,0,0.67] SDP [3,4,3] 1.908 0.326 θ [0,1.333,0] 0.703 0.628 4. SCALABILITY IMPROVEMENT For practical industry instances, we select a subset of ... |

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Citation Context ...ng capacitor insertion for reduced time domain variation of supply voltage. Decoupling capacitances are provided by CMOS capacitors through a thin-oxide layer between an n-well and a polisilicon gate =-=[20]-=-. Decoupling capacitors serve as “charge reservoirs” and form shortcut supply current paths when inserted close to supply voltage degradation hot spots. Reduced supply current path length leads to red... |

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Citation Context ...imization problems such as graph partitioning and quadratic assignment problems [1, 6, 17]. Boyd et al. propose a semidefinite program formulation for VLSI interconnect timing optimization as follows =-=[16]-=-. Minimize t Sub ject to tG −C � 0 (2) where scalar t is an upper bound of the delays of the interconnect system, and � represents the left side matrix M = tG−C is positive semidefinite, i.e., xT Mx ≥... |

11 | Frequency Domain Analysis of Switching Noise
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(Show Context)
Citation Context ...lly do not affect analysis results [2, 9]. Frequency domain techniques, e.g., interconnect model order reduction [10, 11], can be applied for P/G network analysis without significant loss of accuracy =-=[13, 19]-=-, because an RC network acts as a low-pass filter, where node waveforms can be approximated closely by sinusoids [2]. Modified nodal analysis (MNA) in an interconnect is presented in [10]. For smaller... |

7 |
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(Show Context)
Citation Context ...e degradation. From a frequency domain point of view, decouping capacitors form low pass filters, cancel inductance effect and lower P/G network impedance, therefore reduce supply voltage degradation =-=[12]-=-. An early heuristic proposed to insert decoupling capacitors in a P/G network based on a scaling factor and estimate needed decoupling capacitance based on the injected charge at the violation node a... |

1 |
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Citation Context ...inusoids [2]. Modified nodal analysis (MNA) in an interconnect is presented in [10]. For smaller instance sizes and matrix symmetry (which is required by most of current semidefinite program packages =-=[4, 5]-=-) we present a different MNA for a P/G network as follows. We separate P/G network nodes into two categories: nodes of reference voltage, i.e., power/ground pads, and free nodes with variable voltages... |

1 |
Goemans, “Semidefinite Programming
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(Show Context)
Citation Context ...new optimization technique, which finds applications in control systems engineering and relaxations of combinatorial optimization problems such as graph partitioning and quadratic assignment problems =-=[1, 6, 17]-=-. Boyd et al. propose a semidefinite program formulation for VLSI interconnect timing optimization as follows [16]. Minimize t Sub ject to tG −C � 0 (2) where scalar t is an upper bound of the delays ... |