## A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools (2003)

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Venue: | Proc. ACM/IEEE DAC |

Citations: | 10 - 4 self |

### BibTeX

@INPROCEEDINGS{Gupta03acost-driven,

author = {P. Gupta and A. B. Kahng and D. Sylvester and J. Yang},

title = {A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools},

booktitle = {Proc. ACM/IEEE DAC},

year = {2003},

pages = {1621}

}

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### Abstract

As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent, and the entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained with minimum total RET cost. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing that substantial RET costs may be saved while maintaining a given desired level of parametric yield.

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Citation Context ...models and doing explicit transistor sizing as in TILOS [13]. (b) Cost-based delay budgeting methods such as [15] are also applicable. Though simple and fast delay/slack budgeting methods such as ZSA =-=[14]-=- may be applied, they suffer from lack of cost awareness. 3. More accurate correction: Input slew awareness in the yield libraries, and inclusion of interconnect and interconnect variability in the an... |

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Citation Context ...sis models gate delays as random variables but has traditionally suffered from exponential run time complexity with circuit size, due to the dependencies created by re-converging paths in the circuit =-=[10]-=-. • We assume that different levels of OPC can be independently applied to any gate in the design. Corresponding to each level of correction, there is an effective channel length Le f f variation and ... |

29 |
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Citation Context ...ith every level of correction. This correspondence immediately highlights a strong similarity between the integer program (3) and the sizing approach outlined in [12] or the budgeting method given in =-=[15]-=-. Our mapping between gate sizing and MinCorr is depicted in Table 2, and is correct to the extent of assuming additivity as in Equation (1). We will point out in the next section how we can retain pe... |

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Citation Context ...ere is a cost and delay σ associated with every level of correction. This correspondence immediately highlights a strong similarity between the integer program (3) and the sizing approach outlined in =-=[12]-=- or the budgeting method given in [15]. Our mapping between gate sizing and MinCorr is depicted in Table 2, and is correct to the extent of assuming additivity as in Equation (1). We will point out in... |

7 |
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Citation Context ...er rejection of the mask in the inspection tool. The result is unduly low mask throughput and high mask costs. Prohibitively high mask costs motivate the need for design for value (DFV) methodologies =-=[2]-=- that attempt to achieve a requisite level of parametric yield ($ per wafer) while minimizing the total cost incurred, both at the design and process levels. For instance, we may have multiple selling... |

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Citation Context ...or correction are the gates that fanout to a large number of critical paths. Good candidates for decorrection are the gates that fanout to a small number of critical paths. Various approaches such as =-=[13, 12]-=- appear useful here.sNominally Correct SP&R Netlist SSTA Yield target met ? Correction Algorithm SSTA Min Corrected Library EXIT All Correction Libraries All Correction Libraries Figure 3: The design ... |

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Citation Context ...acks at all the primary outputs, then we can approximate the circuit delay distribution by the maximum of all output delay distributions. The mean of the circuit delay distribution is then bounded by =-=[11]-=- n − 1 µcircuit ≤ µout put + σout put √ 2n − 1 Moreover, the variance of the circuit delay is bounded by the variance of the output delay distributions [11], i.e., σcircuit ≤ σout put This gives a way... |

2 |
ASML MaskTools, personal communication
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Citation Context ...in which there may be a wider range of polysilicon gate configurations (bent gates, varied pitches, tapered stack sizes, etc.). An example of the levels of correction we consider is shown in Figure 4 =-=[19]-=-. The variation and cost corresponding to each level of correction is listed in Table 3 [16]. The channel length variations 7 are given relative to the drawn channel length (130nm in our process) and ... |

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1 |
Numerical Technologies Inc., personal communication
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Citation Context ...itches, tapered stack sizes, etc.). An example of the levels of correction we consider is shown in Figure 4 [19]. The variation and cost corresponding to each level of correction is listed in Table 3 =-=[16]-=-. The channel length variations 7 are given relative to the drawn channel length (130nm in our process) and are based on simulation of the polysilicon layer for various types of cells. The figure coun... |

1 |
Intel Corp., personal communication
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Citation Context ...ys translated to major improvements in CD controllability. 7 The variation listed in Table 3 is calculated within-die but we expect die-to-die and within-die variation to be nearly equal in magnitude =-=[20]-=-.sFigure 1: Relative contributions of various components of mask cost. Testcase Normalized Cost Normalized delay alu128 5.0000 (Aggressive OPC) 0.9479 4.0000 (Medium OPC) 0.9623 1.0000 (No OPC) 1.0000... |