## Timing analysis for full-custom circuits using symbolic DC formulations (2006)

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Venue: | IEEE Trans. Computer-Aided Design |

Citations: | 1 - 0 self |

### BibTeX

@ARTICLE{Song06timinganalysis,

author = {Hui-yuan Song and R. Iris Bahar},

title = {Timing analysis for full-custom circuits using symbolic DC formulations},

journal = {IEEE Trans. Computer-Aided Design},

year = {2006},

volume = {25},

pages = {1815--1830}

}

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### Abstract

Successful timing analysis of high-speed integrated circuits requires accurate delay computation. However, full-custom circuits popular in today’s CPU designs make this difficult. In this paper we introduce a symbolic method for computing the delay of these complex MOS circuits by modeling all devices as twoport networks. This approach allows us to handle various circuit structures, including series-parallel and arbitrary meshes, directly without the need to decompose them into simpler circuits first. In addition, the symbolic approach enables efficient computation of the delay as a function of its inputs and can naturally handle exclusivity conditions within the symbolic representation. 1.

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Citation Context ...s. Hence, our combined solution technique is symbolic DC analysis, where the delay for some output node is computed as a function of its inputs and represented using Algebraic Decision Diagrams(ADDs) =-=[1]-=-. Before the details, let’s go over one of the previous work by McDonald and Bryant [10]. They break a CCR’s arbitrary mesh into a tree. This is clearly simpler than dealing with the mesh, but at a lo... |

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Citation Context ... of every possible input combination; however, this is prohibitively expensive for more than a small number of inputs. The Elmore model has been used extensively to compute the delay of MOS circuits (=-=[5, 10, 11, 12, 14, 15]-=- to name a few). This simple delay model approximates a MOS circuit with an RC circuit by decomposing a circuit into simple trees, replacing conducting (ON) devices with linear resistors and modeling ... |

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Citation Context ...es is to assume that the proportionality constant between device width and effective resistance is the same for all devices. In fact, it varies based on the device’s position in the stack [20], [24], =-=[32]-=-. Internal stack nodes on an N-pulldown stack may start out at Vdd − VT n. When the stack first turns on, only the bottom-of-stack device with its source at Vss is on; the other devices, with their so... |

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Citation Context ...on), even on full-custom circuits. The second important application is as a delay model for functional validation of full-custom circuits (most commonly, memories) with Symbolic Trajectory Evaluation =-=[2]-=- (STE). STE uses symbolic logic simulation (i.e., logic simulation with symbolic input patterns) to validate that a circuit-level design produces the correct logic results. STE can take advantage of a... |

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Citation Context ... of every possible input combination; however, this is prohibitively expensive for more than a small number of inputs. The Elmore model has been used extensively to compute the delay of MOS circuits (=-=[5, 10, 11, 12, 14, 15]-=- to name a few). This simple delay model approximates a MOS circuit with an RC circuit by decomposing a circuit into simple trees, replacing conducting (ON) devices with linear resistors and modeling ... |

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Citation Context ... are thus not easily amenable to symbolic analysis, as reported by McDonald [9]. Our approach aims to expand on the symbolic analysis ideas of [10] but instead use an Asymptotic Wave Evaluation (AWE) =-=[13]-=- to better handle circuit structures that are series-parallel, or even arbitrary meshes. We use a twoport network model to avoid splitting the network into trees, thereby enabling us to analyze multip... |

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Citation Context ... of every possible input combination; however, this is prohibitively expensive for more than a small number of inputs. The Elmore model has been used extensively to compute the delay of MOS circuits (=-=[5, 10, 11, 12, 14, 15]-=- to name a few). This simple delay model approximates a MOS circuit with an RC circuit by decomposing a circuit into simple trees, replacing conducting (ON) devices with linear resistors and modeling ... |

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Citation Context ...alidate our algorithm using more complex circuits, we have also used our tool to compute the delay for 3036 real circuits from industry used in the design of the Alpha 21264 and 21364 microprocessors =-=[35]-=-. These circuits implemented a broad variety of functions and included series/parallel as well as mesh networks implemented in either static or dynamic logic. Several also contained feedback within th... |

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Citation Context ...ries-parallel network rather than asSONG et al.: TIMING ANALYSIS FOR FULL-CUSTOM CIRCUITS USING SYMBOLIC DC FORMULATIONS 3 tree. Thus, existing methods calculate its Elmore delay with heuristics [26]–=-=[28]-=-. In [28], Lin and Mead proposed a tree decomposition and capacitance load distribution technique. They break a general RC mesh network into a collection of tree subnetworks and the node capacitance i... |

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Citation Context ...hing becomes still more important in order to keep the total delay-model accuracy reasonable. Static timing analysis has been extensively researched and includes such approaches as those presented in =-=[8, 3, 6, 4, 2]-=-. While these techniques can obtain more accurate delay information by accounting for input slope, timing across latches and crosstalk, these techniques in and of themselves do not take into account i... |

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Citation Context ...hing becomes still more important in order to keep the total delay-model accuracy reasonable. Static timing analysis has been extensively researched and includes such approaches as those presented in =-=[8, 3, 6, 4, 2]-=-. While these techniques can obtain more accurate delay information by accounting for input slope, timing across latches and crosstalk, these techniques in and of themselves do not take into account i... |

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Citation Context ...hing becomes still more important in order to keep the total delay-model accuracy reasonable. Static timing analysis has been extensively researched and includes such approaches as those presented in =-=[8, 3, 6, 4, 2]-=-. While these techniques can obtain more accurate delay information by accounting for input slope, timing across latches and crosstalk, these techniques in and of themselves do not take into account i... |

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Citation Context ... that we have approximated delay with a first moment analysis. We could equally well have used higher-order moments, as was done in [18], [20]. For example, D2M is a delay metric based on two moments =-=[34]-=-. We chose not to implement this, largely because we believe the improved fidelity in analyzing the linearized network with higher-order moments would be hidden by the errors introduced in converting ... |

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Citation Context ...often not the case for large CCRs, where input assignments may be restricted to a subset of input vectors. There has been significant work on symbolic analog simulation. Determinant Decision Diagrams =-=[16]-=- (DDDs) use symbols to replace all parameter values in a circuit. DDD’s take advantage of repeated subexpressions in determinants and can be quite compact. Symbolic AWE [17] allows the user to pick a ... |

13 |
Sport and Community
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Citation Context ...circuits. Furthermore, the heuristics applied depend on knowing a priori which inputs are rising/falling at which times, and are thus not easily amenable to symbolic analysis, as reported by McDonald =-=[9]-=-. Our approach aims to expand on the symbolic analysis ideas of [10] but instead use an Asymptotic Wave Evaluation (AWE) [13] to better handle circuit structures that are series-parallel, or even arbi... |

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9 |
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Citation Context ...lel positive-channel metal oxide semiconductor (PMOS) pullups of a simple NAND gate are a series-parallel network rather than a tree. Thus, existing methods calculate its Elmore delay with heuristics =-=[26]-=-–[28]. In [28], Lin and Mead proposed a tree decomposition and capacitance load distribution technique. They break a general RC mesh network into a collection of tree subnetworks and the node capacita... |

5 |
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Citation Context ...t instances of the same circuit may have different exclusivity constraints, depending on their usage. Glebov et al. give a technique for automatically deducing constraints from a circuit netlist [6], =-=[7]-=-. Formal assertion validation techniques also could be used to validate external constraints. For instance, in assertion-based verification, an architect could assert that no two wordlines of a partic... |

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Citation Context ...compute delay. It is well-known that input slope can have a significant impact on circuit delay, and several methods have been proposed to better account for this effect (e.g., [9], [14], [24], [25], =-=[33]-=-). Intuitively, a fast input slew rate (relative to the output) implies that the devices are fully turned on for a larger portion of the time, and have a higher effective conductance. We chose to impl... |

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Citation Context ...tool, the timing of a CCR’s inputs can also provide exclusivity constraints, as will be discussed in Section VII. Delay modeling and static timing analysis have been extensively researched (e.g., [9]–=-=[15]-=-). While these techniques obtain more accurate delay information by accounting for input slope, timing across latches and crosstalk, they do not consider a circuit’s input exclusivity constraints. The... |

3 |
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Citation Context ...s, while typically keeping device sizes constant. Even if re-analysis is fast, doing it 2 32 times for a CCR with 32 inputs is quite impractical. Multi-terminal Determinant Decision Diagrams (MTDDDs) =-=[18]-=-–[20] extend the concept of DDDs not only by allowing only some (rather than all) component values to be represented by symbols, but also by allowing Boolean symbols that can switch a resistor’s condu... |

3 |
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Citation Context ...es is to assume that the proportionality constant between device width and effective resistance is the same for all devices. In fact, it varies based on the device’s position in the stack [20], [24], =-=[32]-=-. Internal stack nodes on an N-pulldown stack may start out at Vdd − VTn. When the stack first turns on, only the bottomof-stack device with its source at Vss is ON; the other devices, with their sour... |

2 |
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2 | An ADD-based symbolic analysis of leakage current in CMOS circuits
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Citation Context ... fall delay Figure 3. DC Equivalent circuit for the circuit in Figure 1 and its output delay values as a function of its inputs (represented as an ADD). each node as a function of inputs. As shown in =-=[16]-=-, this has already been done in the context of leakage analysis and can be computed in a straightforward manner even for an arbitrary mesh. To calculate the first moment for the falling delay, we mode... |

2 |
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Citation Context ...ferent instances of the same circuit may have different exclusivity constraints, depending on their usage. Glebov et al. give a technique for automatically deducing constraints from a circuit netlist =-=[6]-=-, [7]. Formal assertion validation techniques also could be used to validate external constraints. For instance, in assertion-based verification, an architect could assert that no two wordlines of a p... |

2 |
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Citation Context ...erminant Decision Diagrams [16] (DDDs) use symbols to replace all parameter values in a circuit. DDD’s take advantage of repeated subexpressions in determinants and can be quite compact. Symbolic AWE =-=[17]-=- allows the user to pick a small number of parameter values to be symbolic, leaving the rest numeric, and then combines partitioned matrix techniques with symbolic Gaussian elimination to generate alg... |

1 |
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Citation Context ...Intel Corporation, Hudson, MA 01749 USA. use. SPICE-like simulation is too slow to run on all circuits in the chip, so a quick filter is needed to pick which paths will require more accurate analysis =-=[1]-=-. This filter must be reasonably accurate (to minimize the need to run SPICE), and must avoid gross misestimations (which typically require costly and error-prone user intervention), even on full-cust... |

1 |
circuit verification with symbolic switch-level timing simulation
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Citation Context ...ter to identify candidate paths for more detailed analysis, thus enhancing existing applications such as [24] by handling exclusivity. It can also be used in symbolic trajectory evaluation, enhancing =-=[4]-=-, [5] by making the delay model more accurate. In both applications, it is very useful to have a fast delay model that is robust even for large CCRs with significant exclusivity conditions. ACKNOWLEDG... |

1 |
functional verification for full custom designs,” http://www.synopsys.com/products/acmgr/innlo/espcv.html. et al
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Citation Context ...ay model, where separate gate delays are specified for every input pattern to the gate and then given to a symbolic event-driven simulator [3], [4]. This technique has been commercialized by Synopsys =-=[5]-=-. Timed symbolic logic simulation does not require SPICE-level accuracy; however, it requires that delay models be accurate enough to abstract correct logic behavior, even with self-timed logic. Once ... |

1 | Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing
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Citation Context ...ty constraints. For example, the phase timing of clock-like signals may preclude their simultaneous assertion. Likewise, the timing of other signals may preclude certain charge-sharing configurations =-=[8]-=-. Finally, when the model is integrated into a timing-analysis tool, the timing of a CCR’s inputs can also provide exclusivity constraints, as will be discussed in Section VII. Delay modeling and stat... |

1 |
Multi-terminal determinant decision diagrams: A new approach to semi-symbolic analysis of analog integrated circuits
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Citation Context ... characteristics (e.g., delay) may be represented as a function of the Boolean state of its inputs. This effectively allows us to combine Boolean analysis with timing analysis. Similar to [16], [17], =-=[19]-=-, these Boolean symbolic methods use implicit data structures that model symmetric or repeated substructures in the circuit only once. This makes analysis of such cases as a function of Boolean input ... |

1 | Mixed algebraic and boolean symbolic analysis of switched linear networks: Theory and applications to coupled gate and interconnect delay modeling,” in
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Citation Context ...ile typically keeping device sizes constant. Even if re-analysis is fast, doing it 2 32 times for a CCR with 32 inputs is quite impractical. Multi-terminal Determinant Decision Diagrams (MTDDDs) [18]–=-=[20]-=- extend the concept of DDDs not only by allowing only some (rather than all) component values to be represented by symbols, but also by allowing Boolean symbols that can switch a resistor’s conductanc... |

1 |
Functional Verification for Full Custom Designs
- ESP-CV
(Show Context)
Citation Context ...ay model, where separate gate delays are specified for every input pattern to the gate and then given to a symbolic event-driven simulator [3], [4]. This technique has been commercialized by Synopsys =-=[5]-=-. Timed symbolic logic simulation does not require SPICE-level accuracy; however, it requires that delay models be accurate enough to abstract correct logic behavior, even with self-timed logic. Once ... |