Abstract

Abstruct- We present efficient, optimal algorithms for timing optimization by discrete wire sizing and buffer insertion. Our algorithms are able to minimize a cost function subject to given timing constraints; we focus on minimization of dynamic power dissipation, but the algorithm is also easily adaptable to, for example, area minimization. In addition, the algorithm efficiently computes the complete, optimal power-delay trade-off curve for added design flexibility. An extension of our basic algorithm ac-commodates a generalized delay model which takes into account the effect of signal slew on buffer delay which can contribute substantially to overall delay. To the best of our knowledge, our approach represents the first work on buffer insertion to incorporate signal slew into the delay model while guaranteeing optimality. The effectiveness of these methods is demonstrated experimentally. NOMENCLATURE A routing tree rooted at node U. The left and right children of node v, respec-tively. Tree edge (wire) from node v to its parent. Length of edge e. Capacitance of edge e. Input capacitance of sink 'U. Resistance of edge e. Input capacitance of buffer b. Output resistance of buffer b or gate g. Intrinsic delay of buffer b or gate g. Polarity; usually referring to a signal, p = 1 meaning inverted. Polarity of buffer b; Pb = 1 indicating b is an inverter, Pb = 0 otherwise. Required arrival time of sink node U. Largest possible wire width (1... W are possi-ble). Buffer library. Set of leaves of tree T.

Citations