A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique (2003)
| Venue: | IEEE J. Solid-Sate Circuits |
| Citations: | 8 - 3 self |
BibTeX
@ARTICLE{Chang03a1.4-v,
author = {Dong-young Chang and Un-ku Moon and Senior Member},
title = {A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique},
journal = {IEEE J. Solid-Sate Circuits},
year = {2003},
volume = {38},
pages = {1401--1404}
}
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Abstract
Abstract—A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25–MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35- m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48–dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC’s minimum operating power supply is 1.3 V @ „r € aHW VA and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes. Index Terms—Analog-to-digital converter (ADC), low voltage, opamp-reset switching technique (ORST), pipeline. I.
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