## Buffer insertion for noise and delay optimization (1998)

Venue: | in Proc. Design Automation Conf |

Citations: | 75 - 11 self |

### BibTeX

@INPROCEEDINGS{Alpert98bufferinsertion,

author = {Charles J. Alpert},

title = {Buffer insertion for noise and delay optimization},

booktitle = {in Proc. Design Automation Conf},

year = {1998},

pages = {362--367}

}

### Years of Citing Articles

### OpenURL

### Abstract

Buffer insertion has successfully been applied to reduce delay in global interconnect paths; however, existing techniques only optimize delay and timing slack. With the increasing ratio of coupling to total capacitance and the use of aggressive dynamic logic circuit families, noise is becoming a major design bottleneck. We present comprehensive buffer insertion techniques for noise and delay optimization. Our experiments on a microprocessor design show that our approach fixes all noise violations that were identified by a detailed, simulation-based noise analysis tool. Further, we show that the performance penalty induced by optimizing both delay and noise as opposed to only delay is 2%. 1.

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Citation Context ...n even more pervasive as the ratio of device to interconnect delay continues to decrease. Several works study delay-driven buffer insertion. Closed formed solutions for 2-pin nets are proposed in [1] =-=[4]-=- [5] and [9]. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In [12], Lillis Anirudh Devgan IBM Austin Resea... |

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Citation Context ...rmed solutions for 2-pin nets are proposed in [1] [4] [5] and [9]. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model =-=[10]-=-. In [12], Lillis Anirudh Devgan IBM Austin Research Laboratory Austin, TX 78660 devgan@austin.ibm.com et al. extends this algorithm to simultaneously perform wire sizing, while also minimizing the to... |

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Citation Context ...tions for 2-pin nets are proposed in [1] [4] [5] and [9]. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In =-=[12]-=-, Lillis Anirudh Devgan IBM Austin Research Laboratory Austin, TX 78660 devgan@austin.ibm.com et al. extends this algorithm to simultaneously perform wire sizing, while also minimizing the total numbe... |

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Citation Context ...e as the ratio of device to interconnect delay continues to decrease. Several works study delay-driven buffer insertion. Closed formed solutions for 2-pin nets are proposed in [1] [4] [5] and [9]. In =-=[16]-=-, Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In [12], Lillis Anirudh Devgan IBM Austin Research Laboratory Austin... |

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Citation Context ...ation even more pervasive as the ratio of device to interconnect delay continues to decrease. Several works study delay-driven buffer insertion. Closed formed solutions for 2-pin nets are proposed in =-=[1]-=- [4] [5] and [9]. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In [12], Lillis Anirudh Devgan IBM Austin R... |

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Citation Context ...ced order interconnect analysis (e.g., AWE[13] and RICE[15]). Although the latter is more efficient, it is still too slow to be used within an optimization tool. Instead, we adopt the noise metric of =-=[8]-=-. The rest of the paper is as follows. Section 2 presents notation and definitions. In Section 3, we derive a formula for the maximum wire length such that no noise violation is induced and also prese... |

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Citation Context ...en more pervasive as the ratio of device to interconnect delay continues to decrease. Several works study delay-driven buffer insertion. Closed formed solutions for 2-pin nets are proposed in [1] [4] =-=[5]-=- and [9]. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In [12], Lillis Anirudh Devgan IBM Austin Research ... |

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Citation Context ...pervasive as the ratio of device to interconnect delay continues to decrease. Several works study delay-driven buffer insertion. Closed formed solutions for 2-pin nets are proposed in [1] [4] [5] and =-=[9]-=-. In [16], Van Ginneken develops a dynamic programming algorithm which finds the optimal buffer placement under the Elmore delay model [10]. In [12], Lillis Anirudh Devgan IBM Austin Research Laborato... |

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Citation Context ...d the buffer, then the circuit will function correctly. Noise analysis is typically performed through detailed circuit simulation or through reduced order interconnect analysis (e.g., AWE[13] and RICE=-=[15]-=-). Although the latter is more efficient, it is still too slow to be used within an optimization tool. Instead, we adopt the noise metric of [8]. The rest of the paper is as follows. Section 2 present... |

2 |
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Citation Context ...rom a modern Power PC microprocessor design. Table 1 shows the distribution of the sizes of these nets. To verify BuffOpt, we also ran a detailed, simulation-based noise analysis tool, called 3dnoise =-=[14]-=-. 3dnoise was run both before and after BuffOpt and DOpt.To perform noise analysis, 3dnoise uses accurate moment-matching based techniques that are similar to RICE [15]. #Sinks 1 2 3 4 5-7 8-10 11-20 ... |

1 |
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Citation Context ...f inferior solutions and return S. Figure 8 Find_Cands Procedure(v). Theorem 3 If B = { b} and NM( b) ≥ NM( si) , ∀si ∈ SI , then Algorithm 3 returns an optimal solution to Problem 2. Proof: Refer to =-=[2]-=- for a proof. With multiple buffers in the buffer library, the optimality of Algorithm 3 is no longer guaranteed. However, in practice, Algorithm 3 generates solutions that are very close to optima; o... |