## Simultaneous Gate Sizing and Placement (2000)

Venue: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |

Citations: | 13 - 3 self |

### BibTeX

@ARTICLE{Chen00simultaneousgate,

author = {Wei Chen and Cheng-ta Hsieh and Massoud Pedram},

title = {Simultaneous Gate Sizing and Placement},

journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

year = {2000},

volume = {19},

pages = {206--214}

}

### OpenURL

### Abstract

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k-most critical paths; b) size down the immediate fan-outs of the gates on the k-most critical paths; c) simultaneously reposition and resize the gates on the k-most critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1

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Citation Context ... the matrix of the 2 nd partial derivatives of f. Function f is convex over a convex set Ω containing an interior point if and only if the Hessian matrix F of f is positive semi-definite throughout Ω =-=[10]-=-. For di,j given in equation (6), the Hessian matrix is not guaranteed to be positive semidefinite. So our delay mode is in general non-convex. � 2.3 Timing Analysis Let directed graph G(V, A) represe... |

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Citation Context ...e continuous sizing methods assume that the gate size of each gate type is a continuous variable. As a result, the gate-sizing problem can be formulated as a mathematical programming problem. In TILOS=-=[4]-=-, the area and delay are modeled by posynomial functions and only one gate is sized at a time. In [5], the area and delay of continuously sized gates are modeled piecewise linearly and all gates in th... |

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Citation Context ... delay of continuously sized gates are modeled piecewise linearly and all gates in the circuit are sized simultaneously. Simultaneous gate sizing and wire sizing is solved by Lagrangian relaxation in =-=[6]-=-. In both of these methods, only the gate sizes are adjusted to match the output loads of the gates, but the other dimension of optimization, i.e. adjusting the wire loads of the gates, is completely ... |

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Citation Context ... across the whole chip. The center of mass constraints are commonly used in placement programs that interleave quadratic programming with circuit bi-partitioning. Examples include Gordian [11], Speed =-=[12]-=-. In general L is the number of parts at the current partitioning step (L is a power of two due to recursive bi-partitioning step). 7sTheorem 2 Problem formulation (7) provides a correct statement of ... |

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Citation Context ...sitive fan-in or fan-out cones of the sized gate may change. As a result, the circuit timing analysis must be repeated after each sizing step. The cost of such dynamic timing update is quite high. In =-=[3]-=-, only a small section around the gate that is being sized is considered for timing recalculation to reduce the computation cost. For libraries with a large number of choices for each gate type, this ... |

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Citation Context ... approaches, which attempt to combine certain optimization steps in the traditional design flows into one integrated step. Examples include techniques for simultaneous technology mapping and placement=-=[1]-=-, simultaneous fan-out optimization and Steiner routing[2]. In this paper we present a unification-based algorithm for simultaneous gate sizing and placement of critical sections of a circuit. Gate si... |

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Citation Context ... given at most two sizes for each gate. These sizes are derived from the continuous sizing solution as explained above. This problem is solved using a dynamic programming technique similar to that of =-=[14]-=-. In this way, we avoid the arbitrary and error-prone technique of simply rounding up the continuous sizing solution to a discrete solution. 5.2 Algorithm Flow The main loop of this algorithm consists... |

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Citation Context ...(e+q+2n”) constraints. Although the number of variables and constraints maybe large, this is not a major concern since a Linear Programming problem can be solved very efficiently. We use LP-Solver of =-=[13]-=- to solve (16). Notice however that to improve the runtime of the LP solver, problem formulation (16) can be approximated by using a similar transformation to that which was used to obtain problem for... |

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Citation Context ...age of expanding the search space by doing simultaneous placement and sizing of gates (although we do not optimize all the gates in the circuit in one shot due to the problem complexity). Compared to =-=[8]-=- which formulates the problem of resizing and relocating gates from some initial placements as a piecewise linear program, we use a more accurate timing function and formulate the optimization problem... |

2 |
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Citation Context ... steps in the traditional design flows into one integrated step. Examples include techniques for simultaneous technology mapping and placement[1], simultaneous fan-out optimization and Steiner routing=-=[2]-=-. In this paper we present a unification-based algorithm for simultaneous gate sizing and placement of critical sections of a circuit. Gate sizing, which has a significant impact on the circuit delay,... |

1 |
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Citation Context ...cells evenly across the whole chip. The center of mass constraints are commonly used in placement programs that interleave quadratic programming with circuit bi-partitioning. Examples include Gordian =-=[11]-=-, Speed [12]. In general L is the number of parts at the current partitioning step (L is a power of two due to recursive bi-partitioning step). 7sTheorem 2 Problem formulation (7) provides a correct s... |

1 |
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Citation Context ...lynomial function, GP and GGP can be used to solve them. In this section, we will describe the GP and GGP approach. The GP problem can be solved efficiently by the infeasible interior-point method of =-=[16]-=-. To solve a GGP problem, the original GGP is transformed into a sequence of GP problems by a process commonly referred to as condensation [18]. 6.1 Background A function u(x) is monomial, if it is of... |

1 |
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Citation Context ...results indicate that this GP algorithm leads to an efficient and stable implementation for solving our problem. 6.3 GGP Condensation To solve the GGP problem, we implement the algorithm described in =-=[17]-=-. This algorithm takes advantage of the arithmetic-geometric mean inequality and transforms the original non-convex GGP to a sequence of convex GPs. The GGP algorithm first introduces a new variable. ... |