Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff (1996)
by
Sachin S. Sapatnekar
| Venue: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN |
| Citations: | 14 - 0 self |
BibTeX
@ARTICLE{Sapatnekar96wiresizing,
author = {Sachin S. Sapatnekar},
title = {Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff},
journal = {IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN},
year = {1996},
volume = {15},
pages = {1001--1011}
}
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Abstract
Citations
| 842 | Linear and nonlinear programming - Luenberger - 1984 |
| 147 | TILOS: A Posynomial Programming Approach to Transistor Sizing - Fishburn, Dunlop - 1985 |
| 111 | A new algorithm for minimizing convex functions over convex sets - Vaidya - 1996 |
| 81 | An exact solution to the transistor sizing problem for cmos circuits using convex optimization - Sapatnekar, Rao, et al. - 1993 |
| 62 | Performance-Driven Interconnect Design Based on Distributed RC Delay Model - Cong, Leung, et al. - 1993 |
| 37 | Geometric programming: methods, computations and applications - Ecker - 1980 |
| 26 | Optimal Wiresizing under Elmore Delay Model - Cong, Leung - 1995 |
| 11 | A survey of optimization techniques for integrated-circuit design - Brayton, Hachtel, et al. - 1981 |
| 10 | Signal delay inRC tree networks - Rubenstein, eld, et al. - 1983 |
| 9 | A convex optimization approach to transistor sizing for CMOS circuits - Sapatnekar, Rao, et al. - 1991 |
