Abstract

An important design decision in the implementation of a superscalar processor is the amount of hardware to allocate to the instruction scheduling mechanism. Dy-namic scheduling provides, at the cost of (possibly sub-stantial) additional hardware, the potential to improve upon a static schedule by incorporating run-time inform-ation in the scheduling decision. In this study we model several different scheduling techniques and machine con-figurations. We measure the performance of these mod-els on seven integer and floating point benchmarks taken from the SPEC89 suite. We report the results of these measurements and their implications with respect to the design of high performance superscalar processors. 1

Citations