Statistical Timing Analysis Under Spatial Correlations

Statistical Timing Analysis Under Spatial Correlations (2005)

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by Hongliang Chang , Sachin S. Sapatnekar

Venue:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Citations:	27 - 3 self

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@ARTICLE{Chang05statisticaltiming,
    author = {Hongliang Chang and Sachin S. Sapatnekar},
    title = {Statistical Timing Analysis Under Spatial Correlations},
    journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
    year = {2005},
    volume = {24},
    pages = {1467--1482}
}

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Abstract

Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations. The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis techniques are��and �� are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a PERT-like circuit graph traversal. The run-time of our algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo simulation. On average, for 100nm technology, the errors of mean and standard deviation values computed by the proposed method respectively, and the errors of predicting the��and confidence point are ��and ��respectively. A testcase with about 17,800 gates was solved in about�seconds, with high accuracy as compared to a Monte Carlo simulation that required more than�hours.

Citations

113	Multivariate Statistical Method - MORRISON - 1978
95	First-order incremental block-based statistical timing analysis - Visweswariah, Ravindran, et al.
86	Statistical timing analysis for intra-die process variations with spatial correlations - Agarwal, Blaauw, et al. - 2003
85	The greatest of a finite set of random variables - Clark - 1961
60	A general probabilistic framework for worst case timing analysis - Orshansky, Keutzer - 2002
57	Block-based static timing analysis with uncertainty - Devgan, Kashyap - 2003
47	Analysis and decomposition of spatial variation in integrated circuit processes and devices - Stine, Boning, et al. - 1997
40	Delay variability: sources, impacts and trends - Nassif
37	Statistical timing for parametric yield prediction of digital integrated circuits - Jess, Naidu, et al. - 2003
37	Challenges and opportunities for design innovations in nanometer technologies,” SRC Working Paper - Cong - 1997
32	Impact of Spatial Intrachip Gate Length Variability on the Performance of HighSpeed Digital Circuits - Orshansky, Milor, et al. - 2002
31	Fast statistical timing analysis by probabilistic event propagation - Liou, Cheng, et al.
29	Statistical Delay Calculation: A Linear Time Method - Berkelaar - 1997
27	E.T.A.F.: Gate Sizing Using a Statistical Delay Model - Berkelaar, Jacobs - 2000
26	Design for variability in DSM technologies - Nassif - 2000
23	Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor - Liu, Nassif, et al. - 2000
20	Computation and refinement of statistical bounds on circuit delay - Agarwal, Blaauw, et al. - 2003
20	PERT as an Aid to Logic Design - Kirkpatrick, Clark - 1966
19	Statistical delay computation considering spatial correlations - Agarwal, Blaauw, et al. - 2003
19	TAU: Timing analysis under uncertainty - Bhardwaj, Vrudhula, et al.
16	Timing Analysis of Combinational Circuits Including Capacitive Coupling and - Choi, Walker - 2000
10	A statistical static timing analysis considering correlations between delays - Tsukiyama, Tanaka, et al. - 2001
4	Timing Yield Calculation Using an Impulse-Train Approach - Naidu - 2002
3	Statistical aspects of modern IC designs - Axelrad, Kibarian - 1998
3	A Large-Scale Fixed-Die Placer from UCLA. Available at: http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/ Placement - Capo
1	False-path-aware statis timing analysis and efficient path selection for delay testing and timing validation - Liou, Krstic, et al. - 2002
1	Test structures for delay variability,” (Personal communication - Boning, Panganiban, et al.