A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR

A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR (2005)

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by Jipeng Li , Gil-cho Ahn , Student Member , Dong-young Chang , Un-ku Moon , Senior Member

Venue:	IEEE J. Solid-State Circuits
Citations:	5 - 3 self

BibTeX

@ARTICLE{Li05a0.9v,
    author = {Jipeng Li and Gil-cho Ahn and Student Member and Dong-young Chang and Un-ku Moon and Senior Member},
    title = {A 0.9V 12mW 5MSPS algorithmic ADC with 77dB SFDR},
    journal = {IEEE J. Solid-State Circuits},
    year = {2005},
    volume = {40},
    pages = {960--969}
}

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Abstract

Abstract—An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR,

Citations

34	A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic adc - Lee - 1994
33	A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3 µm CMOS - Lin, Kim, et al.
22	Digital-Domain Calibration of Multistep Analog-to-Digital Converters - Lee, Song - 1992
22	An Improved Frequency Compensation Technique for CMOS Operational Amplifiers - Ahuja
20	Background digital calibration techniques for pipelined ADC’s - Moon, Song - 1997
19	An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration - Ming, Lewis - 2001
15	A 15-b, 5-Msample/S low-spurious CMOS ADC - Kwak, Song, et al. - 2001
14	Switched opamp: An approach to realize full CMOS SC circuits at very low supply voltages - Crols, Steyaert - 1994
13	Background calibration techniques for multistage pipelined ADC’s with digital redundancy - Li, Moon - 2003
13	A 13-b 10-Msample/s ADC digitally calibrated with oversampling Delta-Sigma converter - Shu, Song, et al. - 1995
13	Gain error correction technique for pipelined analogue-to-digital converters,” Electron - Siragusa, Galton - 2000
11	S’92–M’94–SM’99) received the B.S. degree from the University of - Moon - 1987
8	A 1.4-V 10-bit 25 MS/s pipelined ADC using opamp-reset switching technique - Chang, Moon - 2003
7	A 0.9 V 9 mW 1 MSPS digitally calibrated ADC with 75 dB - Chang, Ahn, et al. - 2003
7	Interstage gain proration technique for digitaldomain multistep ADC calibration - Lee, Song - 1994
7	to August 1989, he was a Member of Technical Staff at AT&T Bell Laboratories - From - 1988
6	1.2-V CMOS switched-capacitor circuits - Wu, Chang, et al. - 1996
5	A self-calibrating 15-b CMOS A/D converter - Lee, Hodges, et al. - 1984
3	to 2001, he was a Design Engineer with Samsung Electronics, Kiheung, Korea, working on mixed analog–digital integrated circuits - From - 1996
2	A 1-V 10MHz clock rate 13-bit CMOS modulator using unit-gain-reset opamps - Keskin, Moon, et al. - 2002
2	received the Outstading Student Paper Award from the - Chang - 2000
1	Bidari et al., “Low-voltage switched capacitor circuits - unknown authors - 1999
1	al.: A 0.9-V 12-mW 5-MSPS ALGORITHMIC ADC WITH 77-dB SFDR 969 [6 - et - 1999
1	20] O. Erdogan et al., “A 12-b digital-background-calibrated algorithmic ADC with 0WH �f THD - Dec - 1997
1	he was with ZTE Corporation, Shanghai, designing RF transceivers for GSM base station systems. From September 1999 to October 2003, he was working toward the Ph.D. degree at Oregon State University. His doctoral research focused on accuracy enhancement te - From - 1998
1	degrees in electronic engineering from Sogang University, Seoul, Korea, and the Ph.D. degree in electrical and computer engineering from - S - 1995
1	where he was engaged in the design of analog front-end systems for CCD/CMOS image sensors and LCD displays. During the summer of 2000, he was with Lucent Technologies, Bell Laboratories - Electronics, Kiheung, et al. - 1997
1	he has been with Oregon State University, Corvallis. His research has been in the area of analog and mixed analog–digital integrated circuits. His past work includes highly linear and tunable continuous-time filters, telecommunication circuits including t - Since - 1998