## Thermal via placement in 3D ICs (2005)

Venue: | in Proceedings of the International Symposium on Physical Design |

Citations: | 18 - 5 self |

### BibTeX

@INPROCEEDINGS{Goplen05thermalvia,

author = {Brent Goplen},

title = {Thermal via placement in 3D ICs},

booktitle = {in Proceedings of the International Symposium on Physical Design},

year = {2005},

pages = {167--174}

}

### OpenURL

### Abstract

As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the thermal resistance of the chip itself. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional 2D ICs. In this paper, thermal vias are assigned to specific areas of a 3D IC and used to adjust their effective thermal conductivities. The thermal via placement method makes iterative adjustments to these thermal conductivities in order to achieve a desired maximum temperature objective. Finite element analysis (FEA) is used in formulating the method and in calculating temperatures quickly during each iteration. As a result, the method efficiently achieves its thermal objective while minimizing the thermal via utilization.

### Citations

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- 2001
(Show Context)
Citation Context ...an spreading out over a larger area, the chip space is better utilized, interconnects are decreased, and transistor packing densities are increased, leading to better performance and power efficiency =-=[2]-=-. Despite the advantages that 3D ICs have over 2D ICs, thermal effects are expected to be more pronounced because of higher power densities and greater thermal resistance along heat dissipation paths.... |

75 | Efficient thermal placement of standard cells in 3D ICs using a force directed approach
- Goplen, Sapatnekar
- 2003
(Show Context)
Citation Context ... exists when convective, isothermal, and/or insulating boundary conditions are appropriately applied. The nature of the packaging and heat sink determines the boundary conditions. The FEA method from =-=[10]-=- was used for temperature calculations in these experiments. An overview of this method, as applied to 3D ICs, is presented in the remainder of this section. 3.1. FEA Background In finite element anal... |

22 | Compact modeling and spice-based simulation for electrothermal analysis of multilevel ulsi interconnects
- Chiang, Banerjee, et al.
(Show Context)
Citation Context ...fective thermal resistances and potential thermal problems [6]. A number of papers have addressed the potential of integrating thermal vias directly inside chips to reduce thermal problems internally =-=[6,7,8,9]-=-. Because of the many dielectric layers, thermal problems are greater and thermal vias can have a larger impact in 3D ICs than 2D ICs. In addition, interconnect structures can create efficient thermal... |

18 |
Thermal analysis of three-dimensional (3-D) integrated circuits (ICs
- Rahman, Reif
(Show Context)
Citation Context ...fective thermal resistances and potential thermal problems [6]. A number of papers have addressed the potential of integrating thermal vias directly inside chips to reduce thermal problems internally =-=[6,7,8,9]-=-. Because of the many dielectric layers, thermal problems are greater and thermal vias can have a larger impact in 3D ICs than 2D ICs. In addition, interconnect structures can create efficient thermal... |

18 |
Thermal analysis of heterogeneous 3-D ICs with various integration schemes
- Chiang, Souri, et al.
- 2001
(Show Context)
Citation Context ...fective thermal resistances and potential thermal problems [6]. A number of papers have addressed the potential of integrating thermal vias directly inside chips to reduce thermal problems internally =-=[6,7,8,9]-=-. Because of the many dielectric layers, thermal problems are greater and thermal vias can have a larger impact in 3D ICs than 2D ICs. In addition, interconnect structures can create efficient thermal... |

10 |
A First Course
- logan
- 2006
(Show Context)
Citation Context ...nd added to the global system of equations. In FEA, these stamps are called element stiffness matrices, [k c], and can be derived as follows using the variational method for an arbitrary element type =-=[11]-=-: T [ k ] = [ B ] [ D ][ B ] c ∫∫∫ V dV ⎡K x ⎢ ⎢ where [ D] = ⎢ 0 ⎢ ⎢ ⎣ 0 0 K y 0 0 ⎤ ⎥ ⎥ 0 ⎥ and Kx, Ky, and Kz are the thermal ⎥ K ⎥ z ⎦ conductivities in the x, y, and z directions. 3.2. Applicatio... |

8 |
Effect of Via Separation and
- Chiang, Banerjee, et al.
- 2000
(Show Context)
Citation Context ...ang et al. first suggested that “dummy thermal vias” can be added to the chip substrate as additional electrically isolated vias to reduce effective thermal resistances and potential thermal problems =-=[6]-=-. A number of papers have addressed the potential of integrating thermal vias directly inside chips to reduce thermal problems internally [6,7,8,9]. Because of the many dielectric layers, thermal prob... |

5 |
Analysis of Thermal Vias
- Lee, Lemczyk, et al.
- 1992
(Show Context)
Citation Context ...ments of thermal vias in the packaging of multichip modules (MCMs) and found that as the size of thermal via islands increased, more heat removal was achieved but less space was available for routing =-=[3]-=-. Li studied the relationships between design parameters and the thermal resistance of thermal via clusters in PCBs and packaging [4]. These relationships were determined by simplifying the via cluste... |

5 |
Optimization of Thermal Via Design Parameters Based on an Analytical Thermal Resistance Model
- Li
- 1998
(Show Context)
Citation Context ...heat removal was achieved but less space was available for routing [3]. Li studied the relationships between design parameters and the thermal resistance of thermal via clusters in PCBs and packaging =-=[4]-=-. These relationships were determined by simplifying the via cluster into parallel networks using the observation that heat transfer is much more efficient vertically through the thickness than latera... |

4 |
Development of a Viable 3D
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- 2001
(Show Context)
Citation Context ...ttempts to overcome some of these limitations by stacking multiple active layers into a monolithic structure, using special processing technologies such as silicon-on-insulator (SOI) or wafer bonding =-=[1]-=-. By expanding vertically rather than spreading out over a larger area, the chip space is better utilized, interconnects are decreased, and transistor packing densities are increased, leading to bette... |

4 |
Thermal Characterization of Vias Using Compact Models
- Pinjala, Iyer, et al.
- 2000
(Show Context)
Citation Context ... that heat transfer is much more efficient vertically through the thickness than laterally from heat spreading. Pinjala et al. performed further thermal characterizations of thermal vias in packaging =-=[5]-=-. Chiang et al. first suggested that “dummy thermal vias” can be added to the chip substrate as additional electrically isolated vias to reduce effective thermal resistances and potential thermal prob... |