## Repeater Design to Reduce Delay and Power in Resistive Interconnect (1998)

Venue: | IEEE Trans. Circuits Syst. II |

Citations: | 50 - 19 self |

### BibTeX

@INPROCEEDINGS{Adler98repeaterdesign,

author = {Victor Adler and Student Member and Eby G. Friedman and Senior Member},

title = {Repeater Design to Reduce Delay and Power in Resistive Interconnect},

booktitle = {IEEE Trans. Circuits Syst. II},

year = {1998},

pages = {607--616}

}

### Years of Citing Articles

### OpenURL

### Abstract

Abstract—In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current. In order to develop a repeater design methodology, a timing model characterizing a complementary metal–oxide–semiconductor (CMOS) inverter driving a resistance–capacitance (‚g ‚g) ‚g load is presented. The model is based on the Sakurai short-channel-power law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical ‚g loads, this analytical repeater model exhibits a maximum error of 16 % as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus tapered-buffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and taperedbuffer repeaters even with relatively small resistive ‚g loads. An expression for the short-circuit power dissipation of a repeater driving an ‚g load is presented. A comparison of the short-circuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made. Index Terms — Buffer insertion, delay optimization, RC interconnect, repeaters.

### Citations

469 |
Circuits, Interconnects and Packaging for VLSI
- Bakoglu
- 1990
(Show Context)
Citation Context ...connections have become increasingly significant. With a linear increase in length, interconnect delay increases quadratically due to a linear increase in both interconnect resistance and capacitance =-=[1]-=-, [2]. Also, large interconnect loads not only affect performance, but degrade the waveform shape, causing excessive short-circuit power to be dissipated in the stage loading a CMOS logic gate. Severa... |

464 | Low-power CMOS digital design
- Chandrakasan, Sheng, et al.
- 1992
(Show Context)
Citation Context ...RCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 5, MAY 1998 Fig. 1. A CMOS inverter driving an RC load. become an increasingly important factor in the circuit design process =-=[15]-=-. For example, clock distribution networks can account for 40% of the total power dissipated on-chip [16]. A high performance clock distribution network can contain many thousands of repeaters due to ... |

396 |
The transient response of damped linear networks
- Elmore
- 1948
(Show Context)
Citation Context ...ibits an accuracy within 15%. The information describing the waveform shape permits a more accurate delay estimation as compared to estimating the path delay based on the classical Elmore delay model =-=[19]-=-. Since the Elmore delay adds the products of a resistor (composed of the sum of the linearized model of an inverter and the interconnect resistance) and all of its downstream capacitors, the Elmore d... |

307 |
Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas
- Sakurai, Newton
- 1990
(Show Context)
Citation Context ... is presented for determining the number and size of the repeaters to attain the minimum propagation delay based on an analytical expression derived from the -power law model for shortchannel devices =-=[13]-=-, [14]. Using the -power law model permits the development of a repeater design methodology that considers the short-channel transistor effect of velocity saturation which is not considered in any of ... |

175 |
Digital Integrated Circuits
- Rabaey, Chandrakasan, et al.
- 2002
(Show Context)
Citation Context ...s: is the gate capacitance of the final buffer in the repeater; is the input gate capacitance of a minimum-size inverter; and is the propagation delay of a minimum-size inverter driving a capacitance =-=[24]-=- since the tapering factor is assumed to be . For each tapered buffer, the final inverter stage is of size and the number of stages in the repeater is (note that this value must be rounded to an integ... |

169 |
Short-Circuit Dissipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits
- Veendrick
- 1984
(Show Context)
Citation Context ...or a 5% increase in delay. Note that the maximum short-circuit power savings occurs when the input transition time of each repeater is approximately equal to the repeater output transition time [24], =-=[30]-=-. VII. CONCLUSION A closed form timing model of a CMOS inverter driving a resistive-capacitive load based on the -power law device model has been presented. This new analytical expression differs from... |

78 | Wire segmenting for improved buffer insertion
- Alpert, Devgan
- 1997
(Show Context)
Citation Context ... and without area constraints [9]. However, the repeater is modeled as a simple resistor and capacitor and no closed form solution is developed. Other repeater insertion methods are described in [10]–=-=[12]-=-. In this paper, CMOS inverting repeaters are presented as a simple yet effective way of reducing the total propagation delay and transition time characteristics of a system with highly resistive inte... |

75 |
J.D.Meindl, "Optimal Interconnection Circuits for VLSI
- Bakoglu
- 1985
(Show Context)
Citation Context ...@ee.rochester.edu; friedman@ee.rochester.edu). Publisher Item Identifier S 1057-7130(98)03962-7. 1057–7130/98$10.00 © 1998 IEEE and output resistance based on the geometric size of the repeaters [1], =-=[3]-=-. Bakoglu equalizes the delay of the repeaters and the interconnect delay to optimize the number and size of the repeaters for a specific resistance–capacitance (RC) interconnect impedance. In [4] and... |

46 |
Optimum Buffer Circuits for Driving Long Uniform Lines
- Dhar, Franklin
- 1991
(Show Context)
Citation Context ...o operate correctly. Dhar and Franklin present a mathematical treatment for optimal repeater insertion in which elegant solutions are described to optimize repeaters with and without area constraints =-=[9]-=-. However, the repeater is modeled as a simple resistor and capacitor and no closed form solution is developed. Other repeater insertion methods are described in [10]–[12]. In this paper, CMOS inverti... |

35 |
A unified design methodology for CMOS tapered buffers
- Cherkauer, Friedman
- 1995
(Show Context)
Citation Context ...citive line is optimally driven by a tapered buffer [see Fig. 9(a)] [1], [21], a highly capacitive and moderately resistive line may possibly be more efficiently driven by a series of tapered buffers =-=[22]-=-, [23]. The application of uniform repeaters versus tapered buffers and tapered-buffer repeaters on an RC line is therefore discussed in this section. An estimate of the total delay of a tapered-buffe... |

28 |
Scheinberg “Short-Circuit Power Dissipation Estimation for CMOS Logic Gates
- Vemuru, N
- 1994
(Show Context)
Citation Context ...emier issues in VLSI circuit design. There are two primary contributions to the total transient power dissipated by a CMOS inverter: dynamic power dissipation and short-circuit power dissipation [25]–=-=[31]-=-. Dynamic power dissipation is quantified by the familiar expression , and in repeater chains is due to the input capacitance of each repeater. On the other hand, shortcircuit power is often neglected... |

26 |
et al., “A 200-MHz 64-b Dual-Issue CMOS Microprocessor
- Dobberpuhl
- 1992
(Show Context)
Citation Context ...rter driving an RC load. become an increasingly important factor in the circuit design process [15]. For example, clock distribution networks can account for 40% of the total power dissipated on-chip =-=[16]-=-. A high performance clock distribution network can contain many thousands of repeaters due to the distributed RC nature of a clock tree. Thus, power consumption must be both accurately estimated and ... |

24 | Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load
- Adler, Friedman
- 1997
(Show Context)
Citation Context ...ad. Note, however, if the input waveform increases more slowly or the load impedance is small, the inverter operates in the saturation region for a longer time before switching into the linear region =-=[17]-=-. Only the falling output (rising input) waveform is considered in this analysis. The following analysis, however, is equally applicable to a rising output (falling input) waveform. The lumped load is... |

20 |
A.:“Modelling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits
- Sichman, Hodges
- 1986
(Show Context)
Citation Context ...citance (RC) interconnect impedance. In [4] and [5], Wu and Shiau describe a repeater implementation to reduce interconnect delay. Their method uses a linearized form of the Shichman–Hodges equations =-=[6]-=- at a specific operating point to determine the proper repeater insertion locations. Nekili and Savaria consider optimal methods for driving resistive interconnect in [7]. They introduce the concept o... |

18 |
Comments on ‘An optimized output stage for MOS integrated circuits
- Jaeger
- 1975
(Show Context)
Citation Context ...hly capacitive and nonnegligibly resistive may exhibit characteristics similar to a purely capacitive line. Since a purely capacitive line is optimally driven by a tapered buffer [see Fig. 9(a)] [1], =-=[21]-=-, a highly capacitive and moderately resistive line may possibly be more efficiently driven by a series of tapered buffers [22], [23]. The application of uniform repeaters versus tapered buffers and t... |

15 |
Osburn “Analysis of the Effects of Scaling on Interconnect Delay in ULSI Circuits
- Bothra, Rogers, et al.
- 1993
(Show Context)
Citation Context ...ctions have become increasingly significant. With a linear increase in length, interconnect delay increases quadratically due to a linear increase in both interconnect resistance and capacitance [1], =-=[2]-=-. Also, large interconnect loads not only affect performance, but degrade the waveform shape, causing excessive short-circuit power to be dissipated in the stage loading a CMOS logic gate. Several met... |

11 | Estimation of short− circuit power dissipation for static CMOS gates," IEICE Trans. on fundamentals of electronics, communication and computer sciences - Hirata, Onodera, et al. - 1996 |

8 |
The simulation of MOS integrated circuits using SPICE2
- Vladimirescu, Liu
- 1980
(Show Context)
Citation Context ...en in Laplace form, is where is the saturation conductance. Equation (3) yields The output voltage of a short-channel inverter driving an RC load is described by (4). This result is compared to SPICE =-=[18]-=- for various RC loads in Fig. 3 and exhibits an accuracy within 15%. The information describing the waveform shape permits a more accurate delay estimation as compared to estimating the path delay bas... |

7 |
Optimal Methods of Driving Interconnections in VLSI Circuits", P a . Intl. Swp. Circuits and Systems
- Nekili, Savaria
- 1992
(Show Context)
Citation Context ...the Shichman–Hodges equations [6] at a specific operating point to determine the proper repeater insertion locations. Nekili and Savaria consider optimal methods for driving resistive interconnect in =-=[7]-=-. They introduce the concept of parallel regeneration in [8] in which precharge circuitry is added to the repeaters to decrease the evaluation time. Although this technique requires fewer repeaters, e... |

4 |
Cmos transistor sizing for minimization of energy-delay product
- Tretz
- 1996
(Show Context)
Citation Context ... with and without area constraints [9]. However, the repeater is modeled as a simple resistor and capacitor and no closed form solution is developed. Other repeater insertion methods are described in =-=[10]-=-–[12]. In this paper, CMOS inverting repeaters are presented as a simple yet effective way of reducing the total propagation delay and transition time characteristics of a system with highly resistive... |

3 |
Modeling the cmos short-circuit power dissipation
- Bisdounis, Nikolaidis, et al.
- 1996
(Show Context)
Citation Context ...he premier issues in VLSI circuit design. There are two primary contributions to the total transient power dissipated by a CMOS inverter: dynamic power dissipation and short-circuit power dissipation =-=[25]-=-–[31]. Dynamic power dissipation is quantified by the familiar expression , and in repeater chains is due to the input capacitance of each repeater. On the other hand, shortcircuit power is often negl... |

2 | Transistor sizing in CMOS logic chains to minimize energy-delay product - Zukowski, Tretz - 1996 |

2 |
Timing and power models for CMOS repeaters driving resistive interconnect
- Adler, Friedman
- 1996
(Show Context)
Citation Context ...shold voltage and the P-channel threshold voltage, . The area defined by this triangle is , which models the total short-circuit current sourced by a CMOS inverter due to a nonstep input signal [17], =-=[29]-=-. The total short-circuit current multiplied by and is the short-circuit power. The short-circuit power dissipation of the following stage for one transition (either rising or falling edge) can theref... |

1 |
Accurate speed improvement techniques for RC line and tree interconnections
- Wu, Shiau
- 1990
(Show Context)
Citation Context ...1], [3]. Bakoglu equalizes the delay of the repeaters and the interconnect delay to optimize the number and size of the repeaters for a specific resistance–capacitance (RC) interconnect impedance. In =-=[4]-=- and [5], Wu and Shiau describe a repeater implementation to reduce interconnect delay. Their method uses a linearized form of the Shichman–Hodges equations [6] at a specific operating point to determ... |

1 |
models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
- “Delay
- 1990
(Show Context)
Citation Context ... Bakoglu equalizes the delay of the repeaters and the interconnect delay to optimize the number and size of the repeaters for a specific resistance–capacitance (RC) interconnect impedance. In [4] and =-=[5]-=-, Wu and Shiau describe a repeater implementation to reduce interconnect delay. Their method uses a linearized form of the Shichman–Hodges equations [6] at a specific operating point to determine the ... |

1 |
simple short-channel MOSFET model and its application to delay analysis of inverters and series-connected MOSFET’s
- “A
- 1990
(Show Context)
Citation Context ...esented for determining the number and size of the repeaters to attain the minimum propagation delay based on an analytical expression derived from the -power law model for shortchannel devices [13], =-=[14]-=-. Using the -power law model permits the development of a repeater design methodology that considers the short-channel transistor effect of velocity saturation which is not considered in any of the af... |

1 |
of tapered buffers with local interconnect capacitance
- “Design
- 1995
(Show Context)
Citation Context ... line is optimally driven by a tapered buffer [see Fig. 9(a)] [1], [21], a highly capacitive and moderately resistive line may possibly be more efficiently driven by a series of tapered buffers [22], =-=[23]-=-. The application of uniform repeaters versus tapered buffers and tapered-buffer repeaters on an RC line is therefore discussed in this section. An estimate of the total delay of a tapered-buffer repe... |

1 | Statistical estimation of short-circuit power in VLSI circuits - Hill, Kang - 1996 |