## Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine (1995)

### Cached

### Download Links

- [www.ccm.ece.vt.edu]
- [web.cecs.pdx.edu]
- [www.awinn.ece.vt.edu]
- DBLP

### Other Repositories/Bibliography

Venue: | In International Workshop on Field-Programmable Logic and Applications |

Citations: | 22 - 3 self |

### BibTeX

@INPROCEEDINGS{Shirazi95implementationof,

author = {Nabeel Shirazi and Peter M. Athanas and A. Lynn Abbott},

title = {Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine},

booktitle = {In International Workshop on Field-Programmable Logic and Applications},

year = {1995},

pages = {282--292},

publisher = {Springer-Verlag}

}

### OpenURL

### Abstract

Abstract. The two dimensional fast Fourier transform (2-D FFT) is an indispensable operation in many digital signal processing applications but yet is deemed computationally expensive when performed on a conventional general purpose processors. This paper presents the implementation and performance figures for the Fourier transform on a FPGA-based custom computer. The computation of a 2-D FFT requires O(N2 log2N) floating point arithmetic operations for an NxN image. By implementing the FFT algorithm on a custom computing machine (CCM) called Splash-2, a computation speed of 180 Mflops and a speed-up of 23 times over a Sparc-10

### Citations

185 |
Theory and Application
- Rabiner, Gold
- 1975
(Show Context)
Citation Context ...equency domain is then converted back to the spatial domain by doing an inverse Fourier transform. Image and digital signal processing (DSP) applications typically require high calculation throughput =-=[4,10]-=-. The 2-D fast Fourier transform application presented here was implemented for near real-time filtering of video images on the Splash-2 FPGA-based custom computing machine (CCM). This application req... |

102 |
Programmable Logic Data
- Xilinx
- 2001
(Show Context)
Citation Context ...ge of the format needed to be quite large in order to represent very large and small, positive and negative real numbers accurately, and (2) the data path width into one of the Xilinx 4010 processors =-=[14]-=- of Splash-2 is 36 bits wide and real and imaginary operands of a complex number are needed to be input on every clock cycle. Based on these requirements the format in Figure 3 was used. s e f Bit#: 1... |

95 |
Splash 2
- ARNOLD, BUELL, et al.
- 1992
(Show Context)
Citation Context ... k x(0) W x(4) x(2) x(6) x(1) x(5) x(3) x(7) 0 W0 W 0 W W 0 W2 0 W 2 W 0 W 0 W 1 W 2 W3 Stage 1 Stage 2 Stage 3 Figure 2: Decimation-in-Time Eight Point FFT. In order to implement an FFT on Splash-2, =-=[1,2]-=- floating point arithmetic adder/subtracter and multiplier units were selected to satisfy the numerical dynamics of this application [12]. Until recently, any meaningful floating point arithmetic has ... |

73 |
VHDL: Hardware Description and Design
- Lipsett, Schaefer, et al.
- 1989
(Show Context)
Citation Context ... resources and speed of older FPGAs. In addition, mapping difficulties occurred due to the inherent complexity of floating point arithmetic. With the introduction of high level languages such as VHDL =-=[9]-=-, rapid prototyping of floating point formats has become possible making such complex structures more feasible to implement. Although low level design was possible, the strategy used in all applicaX(0... |

69 | Quantitative Analysis of Floating Point Arithmetic on FPGA-based Custom Computing Machines
- Shirazi, Walters, et al.
- 1995
(Show Context)
Citation Context ...me Eight Point FFT. In order to implement an FFT on Splash-2, [1,2] floating point arithmetic adder/subtracter and multiplier units were selected to satisfy the numerical dynamics of this application =-=[12]-=-. Until recently, any meaningful floating point arithmetic has been virtually impossible to implement on FPGA based systems due to the limited density, routing resources and speed of older FPGAs. In a... |

61 |
Real-time Image Processing on a Custom Computing Platform
- Athanas, Abbott
- 1995
(Show Context)
Citation Context ... k x(0) W x(4) x(2) x(6) x(1) x(5) x(3) x(7) 0 W0 W 0 W W 0 W2 0 W 2 W 0 W 0 W 1 W 2 W3 Stage 1 Stage 2 Stage 3 Figure 2: Decimation-in-Time Eight Point FFT. In order to implement an FFT on Splash-2, =-=[1,2]-=- floating point arithmetic adder/subtracter and multiplier units were selected to satisfy the numerical dynamics of this application [12]. Until recently, any meaningful floating point arithmetic has ... |

32 |
Field Programmable Gate Arrays and Floating Point Arithmetic
- Fagin, Renard
- 1994
(Show Context)
Citation Context ...er/subtracter unit could fit into a single Xilinx chip. The 24-bit multiplier needed in single precession floating point multiply can be broken up into four 12-bit multipliers, allocating two per chip=-=[5]-=-. We found that a 16x16 parallel bit multiplier was the largest parallel integer multiplier that could fit into a Xilinx 4010 chip. When synthesized, this multiplier used 75% of the chip area. However... |

4 |
Searching Genetic Databases on
- Hoang
- 1993
(Show Context)
Citation Context ...d can be considered as a general purpose custom computing platform. Applications include pattern matching, text searching and genome data base searching, and many different image processing algorithms=-=[2, 8]-=-. The genome base search implementation has shown a speed-up of three orders of magnitude oversthe MasPar-1. The Splash-2 implementation of a 2-D FFT has shown that the performance is similar to a DSP... |

2 |
A Floating Point Format for Signal
- Eldon, Robertson
- 1982
(Show Context)
Citation Context ...equency domain is then converted back to the spatial domain by doing an inverse Fourier transform. Image and digital signal processing (DSP) applications typically require high calculation throughput =-=[4,10]-=-. The 2-D fast Fourier transform application presented here was implemented for near real-time filtering of video images on the Splash-2 FPGA-based custom computing machine (CCM). This application req... |

2 |
P754. A proposed standard for binary floating-point arithmetic
- Task
- 1981
(Show Context)
Citation Context ...synthesis to generate the FPGA mapping. 3.1 Floating Point Format Representation The floating-point format used in this application is similar the IEEE 754 standard for storing floating point numbers =-=[7]-=-. For the FFT implementation presented here, a smaller 18-bit floating-point format was developed. The format was chosen to accommodate two specific requirements: (1) the dynamic range of the format n... |

1 |
Product Trends and Resource Guide
- Design
- 1995
(Show Context)
Citation Context ...o do and IFFT. The i860 processing board consisted of two, 50 Mhz, i860 chips and 200 Mbytes of RAM. The Sharp DSP chip was chosen since it was the fastest DSP chip surveyed out of almost 60 DSP chips=-=[3]-=-. The Sharp DSP can calculate a complex multiply in one clock cycle at 40 Mhz[11]. The Texas Instruments DSP chip was selected because its performance was about average for the DSP chips in the survey... |

1 |
Fast Fourier Transform,” Sharp Application Note for the LH9124
- Corp
- 1992
(Show Context)
Citation Context ...d 200 Mbytes of RAM. The Sharp DSP chip was chosen since it was the fastest DSP chip surveyed out of almost 60 DSP chips[3]. The Sharp DSP can calculate a complex multiply in one clock cycle at 40 Mhz=-=[11]-=-. The Texas Instruments DSP chip was selected because its performance was about average for the DSP chips in the survey. The algorithm used in the survey to benchmark the DSP chips was a 1024, one dim... |

1 |
An Indoor Wireless Communications Channel Model Implementation on a Custom Computing Platform, VPI&SU Master Thesis in progress
- Walters
(Show Context)
Citation Context ...4.9 MHz Tested Speed 10 MHz 10 MHz TABLE 1. Summary of Properties of 18-bit Floating Point Units. The floating point arithmetic units have also been incorporated in another application: an FIR filter =-=[13]-=-. The FFT application operates at 10 Mhz and the results of the transform are stored in memory on the Splash-2 array board. These results were checked by doing the same transform on a Sparc workstatio... |