Instruction set mapping for performance optimization (1993)
| Venue: | In Proc. of the IEEE/ACM International Conference on Computer-Aided Design |
| Citations: | 10 - 2 self |
BibTeX
@INPROCEEDINGS{Corazao93instructionset,
author = {M. Corazao and M. Khalaf and L. Guerra and M. Potkonjak and J. Rabaey},
title = {Instruction set mapping for performance optimization},
booktitle = {In Proc. of the IEEE/ACM International Conference on Computer-Aided Design},
year = {1993},
pages = {518--521},
publisher = {IEEE Computer Society Press}
}
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Abstract
Pe~ormunce optimization is the primary design goal in most digital signal processing (DSP) and numerically intensive applications. The problem of mapping high-level algorithmic descriptions for these applications to special-ized instruction sets has only recently begun to receive attention. In fact, the problem of optimizing performance has yet to be addressed directly. This paper introduces a new approach to instruction set mapping (and template matching in general) targeted toward pe~ormance optimi-zation. Several novel issues are addressed inc[uding par-tial matching and automatic clock selection. 1
Citations
| 81 | Optimal code generation for expression trees - Aho, Johnson - 1976 |
| 13 | Anatomy of a Silicon Compiler - Brodersen, ed - 1992 |
| 9 | Anatomy of a Hardware Compiler - Keutzer, Wolf - 1988 |
| 1 | Tjiang: “Code Generation Using Tree Ma~ching and L)ynamic Programming - Aho, Ganapathi, et al. - 1989 |
| 1 | Kurdahi: “Partitioning by Regularity Extra - Rae, J - 1991 |
