## Theoretical and practical limits of dynamic voltage scaling (2004)

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Venue: | In DAC ’04: Proceedings of the 41st annual conference on Design automation |

Citations: | 48 - 9 self |

### BibTeX

@INPROCEEDINGS{Zhai04theoreticaland,

author = {Bo Zhai and David Blaauw and Dennis Sylvester and Krisztian Flautner},

title = {Theoretical and practical limits of dynamic voltage scaling},

booktitle = {In DAC ’04: Proceedings of the 41st annual conference on Design automation},

year = {2004},

pages = {868--873},

publisher = {ACM Press}

}

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### Abstract

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum Vdd. However, it is possible to construct designs that operate over a much larger voltage range: from full Vdd to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that for subthreshold supply voltages leakage energy becomes dominant, making “just in time completion” energy inefficient. We derive an analytical model for the minimum energy optimal voltage and study its trends with technology scaling. Second, we use the proposed model to study the workload activity of an actual processor and analyze the energy efficiency as a function of the lower limit of voltage scaling. Based on this study, we show that extending the voltage range below 1/2 Vdd will improve the energy efficiency for most processor designs, while extending this range to subthreshold operation is beneficial only for very specific applications. Finally, we show that operation deep in the subthreshold voltage range is never energy-efficient.

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Citation Context ...d to inverter delay 1. Note that we assume that short circuit power is negligible and can be ignored. This assumption is known to hold for well-designed circuits in normal (super-threshold) operation =-=[13]-=-. Using SPICE simulations we have found that this assumption holds in subthreshold operation as well.sEnergy 10 −12 10 −14 10 −16 different energy components (log scale) 10 0 0.5 1 1.5 2 −20 10 −18 E ... |

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Citation Context ... stretching each task to its deadline, as shown in Figure 1(b). As the processor frequency is reduced, the supply voltage can be reduced. As shown by the equations below 1 , the reduction in frequency=-=[5]-=- combined with a quadratic reduction from the supply voltage results in an approximately cubic reduction of power consumption. However, with reduced frequency the time to complete a task increases, le... |

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Citation Context ...s in workload that are increasingly common in mobile applications. Hence, extensive work has been performed on how to determine voltage schedules that maximize the energy savings obtained from DVS [4]=-=[8]-=-. In most current DVS processor designs, the voltage range is limited from full Vdd to approximately half Vdd at most. In Table 1, the available range of operating voltages and associated performance ... |

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(Show Context)
Citation Context ...ys require the peak performance from the processor. Hence, in a system with a fixed performance level, certain tasks complete ahead of their deadline and the processor enters a low-leakage sleep mode =-=[4]-=- for the remainder of the time. This operation is illustrated in Figure 1(a). Freq f normal 0 Vdd Vdd normal 0 task1 task2 task1 task2 t t (a) (b) Figure 1. Illustration of optimal task scheduling Vdd... |

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Citation Context ...eshold” operating regimes, the supply voltage lies below the threshold voltage and the circuit operates using leakage currents. Work has been reported on designs that operate at subthreshold voltages =-=[6]-=-[7] and it was reported that the ideal minimum allowable supply voltage of a functional CMOS inverter is 36mV [9]. A number of commercial products have also used subthreshold operation for extremely l... |

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Citation Context ...kage currents. Work has been reported on designs that operate at subthreshold voltages [6][7] and it was reported that the ideal minimum allowable supply voltage of a functional CMOS inverter is 36mV =-=[9]-=-. A number of commercial products have also used subthreshold operation for extremely low power applications [10]. With some additional design effort, it is possible to significantly extend the operat... |

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Citation Context ...d that the ideal minimum allowable supply voltage of a functional CMOS inverter is 36mV [9]. A number of commercial products have also used subthreshold operation for extremely low power applications =-=[10]-=-. With some additional design effort, it is possible to significantly extend the operating voltage range of processors. One issue that needs to be addressed is the determination of a lower limit of th... |

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(Show Context)
Citation Context ...l to that of the inverter. It is, however, clear that there are practical reasons why operating circuits at the minimum voltage is not desirable, such as susceptibility to noise and process variations=-=[15]-=-. More importantly, we show in the next section that from an energy efficiency point of view, the minimum operating voltage for functionally correct operation does not provide the best results. 3 Mini... |

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Citation Context ...ng the expression in EQ14 as follows: E total = E active + E leak (EQ 20) 2 E act = α ⋅S HD ⋅C w0 ⋅ W total ⋅ V dd (EQ 21) where SHD is the switching factor to model the hamming distance of the inputs=-=[21]-=-, Wtotal is the total width of all the transistors in the circuit, Cw0 is the capacitance of a unit width transistor. We compute the total leakage energy as follows: E leak = I leak, total ⋅ V dd ⋅ t ... |