## Hotspot: A compact thermal modeling method for CMOS VLSI systems (2006)

Venue: | IEEE Transactions on |

Citations: | 68 - 11 self |

### BibTeX

@ARTICLE{Huang06hotspot:a,

author = {Wei Huang and Student Member and Shougata Ghosh and Siva Velusamy and Karthik Sankaranarayanan and Kevin Skadron and Mircea R. Stan and Senior Member and Senior Member},

title = {Hotspot: A compact thermal modeling method for CMOS VLSI systems},

journal = {IEEE Transactions on},

year = {2006},

volume = {14},

pages = {501--513}

}

### Years of Citing Articles

### OpenURL

### Abstract

Abstract—This paper presents HotSpot—a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient. Index Terms—Compact thermal model, early design stages, interconnect self-heating, temperature, VLSI. I.

### Citations

1098 | Wattch: A framework for architectural-level power analysis and optimizations
- Brooks, Tiwari, et al.
- 2000
(Show Context)
Citation Context ...es are achievable as presented earlier in this section. This is because power estimations at this level (dynamic power with switching factors and static power) are available from tools such as Wattch =-=[33]-=-. Average current loading in the power/gound network can also be roughly estimated by solving a coarse VDD/GND mesh (which is similar to the regular-grid-cell thermal resistive network in HotSpot) wit... |

360 | Temperature-Aware Microarchitecture: Modeling and Implementation
- Skadron, Stan, et al.
- 2004
(Show Context)
Citation Context ... stages. The modeling method is based on the stacked-layer packaging configuration that is predominant in modern VLSI packaging schemes and is an improvement compared with our previous work [4], [6], =-=[7]-=-. 2) We analytically investigate the relationship between the number of nodes in the compact thermal model and the accuracy of the model. For thermal analysis during early design stages, it is importa... |

126 | 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and system-on-chip integration
- Banerjee, Souri, et al.
- 2001
(Show Context)
Citation Context ...thermal paste, silicon substrate, on-chip interconnect layers, C4 pads, ceramic packaging substrate, and solder balls. The recently proposed stacked chip-scale packaging (SCP) [19] and 3-D IC designs =-=[20]-=- are also stacked-layer structures and can be easily modeled as extensions of the generic stack structure in Fig. 2. When deriving a compact thermal model in HotSpot, the different layers, their posit... |

117 | A Stochastic Wire-length Distribution for Gigascale Integration
- Davis, Meindl
- 1998
(Show Context)
Citation Context ...nal interconnects: We predict the average signal interconnect length in each metal layer by adopting and extending the statistical a priori wire-length distribution model presented by Davis et al. in =-=[25]-=-, which improves the wire-length distribution model by Donath [26]. It is important to note that an interconnect thermal model at high levels of abstraction strongly depends on the a priori wire-lengt... |

94 | Compact thermal modeling for temperature-aware design
- Huang, Stan, et al.
(Show Context)
Citation Context ...s to a design methodology that uses temperature as a guideline throughout the design flow. The resulting design can thus be thermally optimized, as it takes into account potential thermal limitations =-=[4]-=-. The major contributions of this work are the following. 1) We propose a modeling methodology—HotSpot—for generating CTMs that can be used in early VLSI design stages where detailed layout is not ava... |

84 | Planning for Performance
- Otten, Brayton
- 1998
(Show Context)
Citation Context ...one section of buffered interconnect , the optimal number of repeaters , and the optimal size of repeaters for interconnects in each region can be found using the repeater insertion model proposed in =-=[29]-=-. The calculations of , , , and are different for wires with or without inserted repeaters—the wire length is either the total wiring net length or the length of a wire section between repeaters; the ... |

66 |
Environment for PowerPC microarchitectural exploration
- Moudgill, Wellman, et al.
- 1999
(Show Context)
Citation Context ...ACROSS-DIE TEMPERATURE DIFFERENCE a thermal package similar to that in Fig. 2. Power dissipation for each on-chip functional unit is estimated from IBM’s cycle accurate Turandot performance simulator =-=[40]-=- and PowerTimer power modeling tool [41]. Here, we can see that TIM thickness significantly affects the temperature difference across the die. Therefore, it is inaccurate to simply model the bottom su... |

54 |
The interpretation and application of Rent's rule
- Christie, Stroobandt
- 2000
(Show Context)
Citation Context ...future designs’ wirelength distributions with good accuracy, as indicated by Rent’s Rule validation data presented in previous works on both traditional and improved Rent’s Rules, such as [25], [27], =-=[30]-=-, [31], [32]. Rent’s Rule is indeed inaccurate for any individual wires, but is quite accurate about aggregate average wire behavior for mature circuit design styles. This is also true about other app... |

52 | Wire Length Distribution for Placement of Computer Logic - Donath - 1981 |

45 | 3-D Thermal-ADI: A Linear-Time Chip Level Transient Thermal Simulator
- Wang
- 2002
(Show Context)
Citation Context ...etailed routing and layout information is not available. There have been several published efforts in full-chip thermal modeling and compact thermal modeling for microelectronics systems. Wang et al. =-=[8]-=- present a detailed and stable die-level transient thermal model based on full-chip layout, solving temperatures for a large number of nodes with an efficient numerical method. The die-level thermal m... |

39 |
ILLIADS-T: An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS
- Cheng
- 1998
(Show Context)
Citation Context ...tailed temperature distribution across the silicon die and can be solved efficiently, but with no information about the transient behavior. An earlier detailed full-chip thermal model by Cheng et al. =-=[11]-=- has an accurate three-dimensional (3-D) model for the silicon and one-dimensional (1-D) model for the package. A significant limitation of the above modeling approaches is the oversimplified thermal ... |

38 | New methodology for earlystage, microarchitecture-level oower-performance analysis of microprocessors
- Brooks, Bose, et al.
- 2003
(Show Context)
Citation Context ...mal package similar to that in Fig. 2. Power dissipation for each on-chip functional unit is estimated from IBM’s cycle accurate Turandot performance simulator [40] and PowerTimer power modeling tool =-=[41]-=-. Here, we can see that TIM thickness significantly affects the temperature difference across the die. Therefore, it is inaccurate to simply model the bottom surface of the silicon as isothermal, as m... |

32 |
Efficient full-chip thermal modeling and analysis
- Li
- 2004
(Show Context)
Citation Context ...ansient thermal model based on full-chip layout, solving temperatures for a large number of nodes with an efficient numerical method. The die-level thermal models by Su et al. in [9] and Li et al. in =-=[10]-=- also provide the detailed temperature distribution across the silicon die and can be solved efficiently, but with no information about the transient behavior. An earlier detailed full-chip thermal mo... |

31 |
Interconnect thermal modeling for accurate simulation of circuit timing and relability
- Chen
- 2000
(Show Context)
Citation Context ...alternatives, where empirical fitting is often not possible [14], [15]. There also have been a number of previous works on thermal modeling of on-chip interconnects and vias. For example, Chen et al. =-=[16]-=- present an interconnect thermal model that closely considers thermal coupling phenomenon between nearby interconnects. This model is accurate but it is on a per-interconnect basis and is not extended... |

29 |
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
- Zarkesh-Ha
- 2000
(Show Context)
Citation Context ...i.e., there are different Rent’s Rule parameters for different subcircuit blocks, then equivalent Rent’s Rule parameters can be found using the heterogeneous Rent’s Rule proposed by Zarkesh-Ha et al. =-=[27]-=-. Three wire-length regions are considered in [25]—local, semi-global, and global. The model predicts the number of wires of any specific length, which is called the interconnect density function , wh... |

26 |
Global (Interconnect) Warming
- Banerjee, Mehrotra
- 2001
(Show Context)
Citation Context ...h-level interconnect self-heating model has been unavailable for early design stages. Most existing interconnect self-heating power and thermal models are either based on analysis of only a few wires =-=[23]-=- or need full-chip detailed layout information that is not available during early design stages [24]. There are two aspects to be considered in the interconnect model: 1) the average self-heating powe... |

23 | Temperature-aware computer systems: opportunities and challenges
- Skadron, Stan, et al.
(Show Context)
Citation Context ... are: HotSpot compact thermal models have been used to close the loop of leakage power calculation [3], explore different architecture-level run-time dynamic thermal management (DTM) techniques [34], =-=[37]-=-, aid the analysis of state-of-the-art computer architectures [38], and perform temperature-aware electromigration (EM) analysis for more accurate interconnect lifetime predictions [39]. Apart from th... |

20 | System level leakage reduction considering the interdependence of temperature and leakage
- HE, LIAO, et al.
- 2004
(Show Context)
Citation Context ... to the thermal ‚g time constants compared with the vertical thermal resistances. Fig. 4. Modeling at the granularity of (a) functional blocks, (b) uniform grid cells, and (c) hybrid-sized grid cells =-=[2]-=-. Fig. 5. (a) A 1-D slab of material with left half dissipating power. (b) Temperature distribution along the length of the slab. a hybrid grid scheme that combines both the per-function unit model an... |

18 | HotSpot: A Dynamic Compact Thermal Model at the
- Stan, Skadron, et al.
- 2003
(Show Context)
Citation Context ...esign stages. The modeling method is based on the stacked-layer packaging configuration that is predominant in modern VLSI packaging schemes and is an improvement compared with our previous work [4], =-=[6]-=-, [7]. 2) We analytically investigate the relationship between the number of nodes in the compact thermal model and the accuracy of the model. For thermal analysis during early design stages, it is im... |

18 |
Two benchmarks to facilitate the study of compact thermal modeling phenomena. Components and Packaging Technologies
- Lasance
- 2001
(Show Context)
Citation Context ...not available. Finally, except for [11], none of these models has shown validation from simulations with detailed numerical models or measurements from real designs. On the other hand, Lasance et al. =-=[12]-=-, Sabry [5], and Bosch [13] present package-level compact thermal models extracted from detailed numerical thermal simulations by data fitting. These models are accurate and have the important propert... |

18 |
Analytical thermal model for multilevel VLSI interconnects incorporating via effect
- Chiang, Banerjee, et al.
- 2002
(Show Context)
Citation Context ...g phenomenon between nearby interconnects. This model is accurate but it is on a per-interconnect basis and is not extended to model multilevel structure at a higher design abstraction. Chiang et al. =-=[17]-=- describe an analytical multilevel interconnect thermal model with considerations of via effects. This model copes with the thermal effect of vias by lumping the heat transferred through the vias into... |

18 | Interconnect lifetime prediction under dynamic stress for reliability-aware design
- Lu
- 2004
(Show Context)
Citation Context ...chniques [34], [37], aid the analysis of state-of-the-art computer architectures [38], and perform temperature-aware electromigration (EM) analysis for more accurate interconnect lifetime predictions =-=[39]-=-. Apart from the above published applications of HotSpot, here we show the importance of modeling packaging components (e.g., thermal interface material (TIM), heat spreader and heat sink) in greater ... |

16 |
The development of component-level thermal compact models of a C4/CBGA interconnect technology: The motorola PowerPC
- Parry, Rosten, et al.
- 1998
(Show Context)
Citation Context ...for it to be useful. First, it should provide detailed temHUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 503 Fig. 2. Stacked layers in a typical ceramic ball grid array (CBGA) package =-=[18]-=- perature distribution at the desired level of abstraction (e.g., a single node representing the die temperature is unacceptable for thermal modeling at the IC level). In addition, both static and tra... |

15 | The need for a full-chip and package thermal model for thermally optimized IC designs
- HUANG, HUMENAY, et al.
- 2005
(Show Context)
Citation Context ...0.00 © 2006 IEEE example, knowing the across-die temperature distribution at design time permits thermally self-consistent leakage power calculations in an iterative manner, as shown in Fig. 1(a) [1]–=-=[3]-=-. Similarly, an efficient thermal model can also help to close the loop for temperature-aware performance and reliability analysis, as suggested in Fig. 1(b). In particular, it is crucial to take ther... |

15 |
Constricting/spreading resistance model for electronics packaging
- Lee, Song, et al.
- 1995
(Show Context)
Citation Context ...rparts due to the fact that the lateral heat-transfer cross-sectional areas are usually much less than vertical ones. We calculate the spreading/constriction resistance based on the formulas given in =-=[21]-=-. The resistance is a spreading one if the lateral area of the source is smaller than the bulk lateral area, and it is a constriction one otherwise. For each node, there is also a thermal capacitance ... |

11 |
A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management
- Banerjee, Lin, et al.
- 2003
(Show Context)
Citation Context ...0/$20.00 © 2006 IEEE example, knowing the across-die temperature distribution at design time permits thermally self-consistent leakage power calculations in an iterative manner, as shown in Fig. 1(a) =-=[1]-=-–[3]. Similarly, an efficient thermal model can also help to close the loop for temperature-aware performance and reliability analysis, as suggested in Fig. 1(b). In particular, it is crucial to take ... |

10 | Compact thermal models for electronic systems - Sabry - 2003 |

10 |
Thermal compact models: An alternative approach. Components and Packaging Technologies
- Bosch
- 2003
(Show Context)
Citation Context ...ept for [11], none of these models has shown validation from simulations with detailed numerical models or measurements from real designs. On the other hand, Lasance et al. [12], Sabry [5], and Bosch =-=[13]-=- present package-level compact thermal models extracted from detailed numerical thermal simulations by data fitting. These models are accurate and have the important property of (quasi-)boundary condi... |

10 |
Performance, energy, and thermal considerations for
- Li, Brooks, et al.
- 2005
(Show Context)
Citation Context ...oop of leakage power calculation [3], explore different architecture-level run-time dynamic thermal management (DTM) techniques [34], [37], aid the analysis of state-of-the-art computer architectures =-=[38]-=-, and perform temperature-aware electromigration (EM) analysis for more accurate interconnect lifetime predictions [39]. Apart from the above published applications of HotSpot, here we show the import... |

6 | Thermal and power integrity based power/ground networks optimization
- Wang, Tsai, et al.
- 2004
(Show Context)
Citation Context ...interconnect self-heating power and thermal models are either based on analysis of only a few wires [23] or need full-chip detailed layout information that is not available during early design stages =-=[24]-=-. There are two aspects to be considered in the interconnect model: 1) the average self-heating power of interconnects in each metal layer and 2) the equivalent thermal resistance for metal wires and ... |

6 | Campenhout. A comparison of various terminal-gate relationships for interconnect prediction in vlsi circuits
- Dambre, Verplaetse, et al.
- 2003
(Show Context)
Citation Context ... designs’ wirelength distributions with good accuracy, as indicated by Rent’s Rule validation data presented in previous works on both traditional and improved Rent’s Rules, such as [25], [27], [30], =-=[31]-=-, [32]. Rent’s Rule is indeed inaccurate for any individual wires, but is quite accurate about aggregate average wire behavior for mature circuit design styles. This is also true about other applicati... |

6 |
gMaking visible the thermal behavior of embedded microprocessors on FPGAs: a progress report,h
- Lopez-Buedo, Boemo
- 2009
(Show Context)
Citation Context ...e sensors that are implemented on the FPGA fabric. We use ring oscillators as temperature sensors by exploiting the fact that the frequency of oscillation is approximately proportional to temperature =-=[36]-=-. Calibrations are done for six different sensors placed near the center of each unit on the die. Power consumption for different units is extracted through various methods. Using the floorplan shown ... |

5 |
Localized heating effects and scaling
- Pop, Banerjee, et al.
- 2001
(Show Context)
Citation Context ...ifications of classical heat transfer equations, which underestimates temperature when applied at size scales less than the phonon–phonon mean free path (about 300 nm for silicon at room temperature) =-=[22]-=-. Thus, for granularity analysis at the transistor level, the phonon Boltzmann transport equation (BTE) should be used instead.sHUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 507 Fig. 1... |

3 |
Full chip estimation considering power supply and temperature variations
- Su, Liu, et al.
- 2003
(Show Context)
Citation Context ...d stable die-level transient thermal model based on full-chip layout, solving temperatures for a large number of nodes with an efficient numerical method. The die-level thermal models by Su et al. in =-=[9]-=- and Li et al. in [10] also provide the detailed temperature distribution across the silicon die and can be solved efficiently, but with no information about the transient behavior. An earlier detaile... |

3 | Physically-based compact thermal modeling—achieving parametrization and boundary condition independence
- Huang, Stan, et al.
- 2004
(Show Context)
Citation Context ...ies and material properties), and, hence, are not parameterizable. Parametrization is important for CTMs to be used in exploring new design alternatives, where empirical fitting is often not possible =-=[14]-=-, [15]. There also have been a number of previous works on thermal modeling of on-chip interconnects and vias. For example, Chen et al. [16] present an interconnect thermal model that closely consider... |

3 | Improved a priori interconnect predictions and technology extrapolation in the GTX system
- Cao, Hu, et al.
- 2003
(Show Context)
Citation Context ...ns’ wirelength distributions with good accuracy, as indicated by Rent’s Rule validation data presented in previous works on both traditional and improved Rent’s Rules, such as [25], [27], [30], [31], =-=[32]-=-. Rent’s Rule is indeed inaccurate for any individual wires, but is quite accurate about aggregate average wire behavior for mature circuit design styles. This is also true about other applications of... |

1 |
physical compact thermal modeling
- “Parameterized
- 2005
(Show Context)
Citation Context ...d material properties), and, hence, are not parameterizable. Parametrization is important for CTMs to be used in exploring new design alternatives, where empirical fitting is often not possible [14], =-=[15]-=-. There also have been a number of previous works on thermal modeling of on-chip interconnects and vias. For example, Chen et al. [16] present an interconnect thermal model that closely considers ther... |