16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits
BibTeX
@MISC{Badaroglu_16.6methodology,
author = {Mustafa Badaroglu and Marc Van Heijningen and Vincent Gravot and John Compiet and Stéphane Donnay and Marc Engels and Georges Gielen and Hugo De Man},
title = {16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits},
year = {}
}
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Abstract
Substrate noise degrades the performance of analog circuits integrated on the same substrate with digital circuits. In these mixed-signal ICs, the low cost and lower static power consumption of CMOS logic are shadowed by the larger noise generation due to the large rail-to-rail voltages and the sharp current spikes during switching. We have designed and measured a mixed-signal chip, fabricated in a 0.35µm CMOS process on an epi-type substrate, which allows us to compare several low-noise digital designs in CMOS. Alternative logic families have been proposed such as current-mode logic [1] or self-timed logic which show orders of magnitude noise reduction, however with increasing static power and delay sensitivity respectively. A few publications exist about low-noise digital CMOS design, e.g. CMOS gates with guard wiring and on-chip decoupling [2], where 67 % noise reduction is achieved, but with considerable area penalty due to the additional circuitry and power rails. The test chip (Figure 16.6.1) contains one reference design (REF) and two digital low-noise designs (LN1, LN2) with the same basic architecture, shown in Figure 16.6.2. LN1 employs an optimized clock tree to make the supply current flatter and LN2 employs a separate substrate bias, dual-supply, and on-chip decoupling. REF has an area of 0.362mm 2, a maximum speed of 45MHz and a core power consumption of 112mW at 42MHz and 3.3V. It is possible to disable the I/O pads in order to measure the substrate noise generation from the core logic
Keyphrases
substrate noise reduction synchronous digital circuit experimental verification cmos mixed-signal ic on-chip decoupling maximum speed considerable area penalty test chip magnitude noise reduction several low-noise digital design substrate noise generation optimized clock tree low cost low-noise digital cmos design static power digital circuit large rail-to-rail voltage reference design mixed-signal chip separate substrate bias delay sensitivity epi-type substrate static power consumption cmos logic analog circuit core logic guard wiring sharp current spike mixed-signal ic additional circuitry supply current flatter power rail substrate noise alternative logic family noise reduction noise generation core power consumption digital low-noise design cmos process self-timed logic current-mode logic basic architecture
