The challenges of hardware synthesis from C-like languages (2004)
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| Venue: | In Design Automation and Test in Europe |
| Citations: | 15 - 1 self |
BibTeX
@INPROCEEDINGS{Edwards04thechallenges,
author = {Stephen A. Edwards},
title = {The challenges of hardware synthesis from C-like languages},
booktitle = {In Design Automation and Test in Europe},
year = {2004},
pages = {66--67}
}
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Abstract
MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: concurrency and timing control. Familiarity is the main reason C-like languages have been proposed for hardware synthesis. Synthesize hardware from C, proponents claim, and we will be able to turn a C programmer into a hardware designer. Another common motivation is hardware/software codesign: today’s systems usually contain a mix of hardware and software, and it is often unclear initially which portions to implement in hardware. Here, using a single language should simplify the migration task. C was developed by Dennis Ritchie in the early 1970s [18], it was derived from BCPL [17]. Both languages ’ abstractions
