Effective compiler generation by architecture description (2006)
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| Venue: | IN LCTES ’06: PROCEEDINGS OF THE 2006 ACM SIGPLAN/SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS |
| Citations: | 5 - 1 self |
BibTeX
@INPROCEEDINGS{Farfeleder06effectivecompiler,
author = {Stefan Farfeleder and Andreas Krall and Edwin Steiner and Florian Brandner},
title = {Effective compiler generation by architecture description},
booktitle = {IN LCTES ’06: PROCEEDINGS OF THE 2006 ACM SIGPLAN/SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS},
year = {2006},
pages = {145--152},
publisher = {ACM Press}
}
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Abstract
Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators and compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code. The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.
