## Low-power logic styles: CMOS versus pass-transistor logic (1997)

Venue: | IEEE J. Solid-State Circuits |

Citations: | 74 - 1 self |

### BibTeX

@ARTICLE{Zimmermann97low-powerlogic,

author = {Reto Zimmermann and Wolfgang Fichtner},

title = {Low-power logic styles: CMOS versus pass-transistor logic},

journal = {IEEE J. Solid-State Circuits},

year = {1997},

volume = {32},

pages = {1079--1090}

}

### Years of Citing Articles

### OpenURL

### Abstract

Abstract — Recently reported logic style comparisons based on full-adder circuits claimed complementary passtransistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangementsdemonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-bit adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits, if low voltage, low power, and small power-delay products are of concern. Index Terms — Adder circuits, CPL, complementary CMOS, low-voltage low-power logic styles, pass-transistor