## Pipelined mixed precision algorithms on FPGAs for fast and accurate PDE solvers from low precision components (2006)

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Venue: | In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM |

Citations: | 9 - 2 self |

### BibTeX

@INPROCEEDINGS{Strzodka06pipelinedmixed,

author = {Robert Strzodka},

title = {Pipelined mixed precision algorithms on FPGAs for fast and accurate PDE solvers from low precision components},

booktitle = {In IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM},

year = {2006},

pages = {259--268}

}

### OpenURL

### Abstract

FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper we take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson Problem as a typical PDE example we show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, we adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the Conjugate Gradient solver. We combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA. 1.

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Citation Context ...h between them. Moreover, different iterative solvers can be employed in the two loops. For numerical examination of multigrid solvers in this context and an implementation on graphics processors see =-=[16]-=-. Here we study the pipelined Conjugate Gradient solver with a focus on an efficient hardware implementation, as multigrid methods generate a complex data-flow which is much harder to map to FPGAs. FP... |