Comparison of Noise Tolerant Precharge (NTP) to (2003)
| Venue: | In Great Lakes Symp. VLSI |
BibTeX
@INPROCEEDINGS{Keepers03comparisonof,
author = {Conventional Feedback Keepers and David Harris and Genevieve Breed and Matt Erler and David Diaz},
title = {Comparison of Noise Tolerant Precharge (NTP) to},
booktitle = {In Great Lakes Symp. VLSI},
year = {2003},
pages = {261--264}
}
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Abstract
Dynamic logic requires some sort of keeper to prevent the output node from floating and to provide acceptable noise immunity. A number of recent papers have advocated using a very weak complementary pMOS network in place of the conventional feedback keeper; such a technique is called Noise-Tolerant Precharge (NTP). This paper compares the delay and noise margin of NTP with conventional feedback keepers. Although NTP is more robust in that it can recover from a dynamic noise event, it is also 5-50% slower than conventional feedback keepers with the same static noise margin.
Citations
| 11 | The twin-transistor noise-tolerant dynamic circuit technique - Balamurugan, Shanbhag - 2001 |
| 7 | Dynamic Logic Circuit with Reduced Charge Leakage - D’Souza - 1996 |
| 4 | Dynamic CMOS Circuits with Noise Immunity - Covino - 1997 |
| 2 | 2.5V Novel CMOS Circuit Techniques for a 150MHz Superscalar RISC Processor - Murabayashi, Yamada, et al. - 1996 |
| 1 | Skewed CMOS: Noise Immune High-Performance LowPower Static Circuit Family - Solomatnikov, Somasekhar, et al. |
| 1 | Input Controlled Refresh for Noise Tolerant Dynamic Circuits - Lakshmanan, Sridhar |
