Delay And Area Optimization For Discrete Gate Sizes Under Double-Sided Timing Constraints (1993)
by
Weitong Chuang
,
Sachin S. Sapatnekar
,
Ibrahim N. Hajj
| Venue: | Proc. IEEE Custom Integrated Circuits Conf |
| Citations: | 13 - 2 self |
BibTeX
@INPROCEEDINGS{Chuang93delayand,
author = {Weitong Chuang and Sachin S. Sapatnekar and Ibrahim N. Hajj},
title = {Delay And Area Optimization For Discrete Gate Sizes Under Double-Sided Timing Constraints},
booktitle = {Proc. IEEE Custom Integrated Circuits Conf},
year = {1993},
pages = {9--4}
}
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Abstract
A three-step algorithm is presented for discrete gate sizing problem of delay#area optimization under double-sided timing constraints. The problem is #rst formulated as a linear program. The solution to the linear program is then mapped onto a permissible set. Using this permissible set, the gate sizes are adjusted to satisfy the delaylower and upper bounds simultaneously.
Citations
| 147 | TILOS: A Posynomial Programming Approach to Transistor Sizing - Fishburn, Dunlop - 1985 |
| 36 | Optimization-Based Transistor Sizing - Shyu, Sangiovanni-Vincentelli, et al. - 1988 |
| 30 | Gate sizing in MOS digital circuits with linear programming - Berkelaar, Jess - 1990 |
| 22 | On the circuit implementation problem - Li, Lim, et al. - 1992 |
| 9 | Delay and area optimization in standard-cell design - Lin, Marek-Sadowska, et al. - 1990 |
| 9 | A convex optimization approach to transistor sizing for CMOS circuits - Sapatnekar, Rao, et al. - 1991 |
| 5 | Algorithms for library-speci c sizing of combinational logic - Chan - 1990 |
