Vulnerabilities in Synchronous IPC Designs (2003)
| Venue: | In Proc. IEEE Symposium on Security and Privacy |
| Citations: | 12 - 0 self |
BibTeX
@INPROCEEDINGS{Shapiro03vulnerabilitiesin,
author = {Jonathan S. Shapiro},
title = {Vulnerabilities in Synchronous IPC Designs},
booktitle = {In Proc. IEEE Symposium on Security and Privacy},
year = {2003},
pages = {251--262},
publisher = {IEEE Computer Society Press}
}
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Abstract
Recent advances in interprocess communication (IPC) performance have been exclusively based on thread-migrating IPC designs. Thread-migrating designs assume that IPC interactions are synchronous, and that user-level execution will usually resume with the invoked process (modulo preemption). This IPC design approach offers shorter instruction path lengths, requires fewer locks, has smaller instruction and data cache footprints, dramatically reduces TLB overheads, and consequently offers higher performance and lower timing variance than previous IPC designs. With care, it can be performed as an atomic unit of operation. While the performance of...
