## Expression Synthesis in Process Networks generated by LAURA

Citations: | 1 - 0 self |

### BibTeX

@MISC{Zissulescu_expressionsynthesis,

author = {Claudiu Zissulescu and Bart Kienhuis},

title = {Expression Synthesis in Process Networks generated by LAURA},

year = {}

}

### OpenURL

### Abstract

The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the Expression Compiler that efficiently maps pseudolinear expressions onto a dedicated hardware datapath in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code. 1

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Citation Context ...work. This is due to the presence of complex operations such as multiplication and integer division. The elimination of division and modulo operations from a sequential programs has been discussed in =-=[16, 12]-=-. Also the PICO project [15] employs similar techinques to avoid MOD and DIV operations. Our target is to generate a custom datapath implementation, and hence, additional issues have to be taken into ... |

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Citation Context ...ion that expresses an application in terms of distributed memory and distributed control. Once the process network is created, the individual processes can either be described in Java [4] or C++ code =-=[5]-=-, or as synthesizable VHDL network of processors suitable for mapping onto FPGAs [20]. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write < 10 ns Figure ... |

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Citation Context ...flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code. 1 Introduction The aim of the COMPAAN compiler =-=[8, 18]-=- is to automatically derive a parallel description from a nested loop application written in a standard programming language like C or Matlab. The applications COMPAAN targets are compute kernels that... |

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Citation Context ...dd}@liacs.nl Presented at the 16th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2005), July 23 – 25, 2005, Samos, Greece Abstract The COMPAAN/LAURA =-=[18]-=- tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is ... |

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Citation Context ...trol. Once the process network is created, the individual processes can either be described in Java [4] or C++ code [5], or as synthesizable VHDL network of processors suitable for mapping onto FPGAs =-=[20]-=-. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write < 10 ns Figure 1. Running an IP core efficiently in a LAURA Processor KPN synthesis to hardware is d... |

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Citation Context ...re, taking advantage of today’s research in PSSA compilation techniques [3]. The PSSA form is suitable for optimizations either for a microprocessor [14] or for a reconfigurable platform such as FPGA =-=[17]-=- in which we are interested. For an FPGA platform target, the desired operations are: the reduction of the number of variables used, multiplexer optimizations, bit-width, and LUT synthesis for non lin... |

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Citation Context ...constant divider. 3 Related Work A KPN network generated by COMPAAN may be simulated using software KPN simulators where all expressions that define a polytope are evaluated in a sequential order. In =-=[7]-=-, a similar approach has been tried for a hardware implementation, but for only a very limited set of expressions (no multiplications and pseudo linear operators). To allow for an efficient compilatio... |

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Citation Context ...write MOD terms into DIV terms. There are cases that a DIV term cannot be converted into a MOD term. In such case, we employ modern software compiler techniques to reduce the cost of integer division =-=[1, 9, 10]-=-. These techniques are based on socalled scaled reciprocals. In general, the techniques transform an integer division into a multiplication with a constant and a shifts expressed, see [10]. Also, we c... |

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Citation Context ...odel of computation that expresses an application in terms of distributed memory and distributed control. Once the process network is created, the individual processes can either be described in Java =-=[4]-=- or C++ code [5], or as synthesizable VHDL network of processors suitable for mapping onto FPGAs [20]. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write... |

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Citation Context ...ignals in less than this 10 ns. The control program in the Read and Write units is expressed in terms of parameterized polytopes. By evaluating these, we can support parameterized control in hardware =-=[6, 13]-=-. The parameterized polytopes are repeatedly evaluated at run-time. If a particular iteration is within the space defined by thespolytope, it means that data needs to be read or written. An example of... |

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Citation Context ...work. This is due to the presence of complex operations such as multiplication and integer division. The elimination of division and modulo operations from a sequential programs has been discussed in =-=[16, 12]-=-. Also the PICO project [15] employs similar techinques to avoid MOD and DIV operations. Our target is to generate a custom datapath implementation, and hence, additional issues have to be taken into ... |

1 | Deriving efficient control in process networks with compaan/laura
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Citation Context ...ignals in less than this 10 ns. The control program in the Read and Write units is expressed in terms of parameterized polytopes. By evaluating these, we can support parameterized control in hardware =-=[6, 13]-=-. The parameterized polytopes are repeatedly evaluated at run-time. If a particular iteration is within the space defined by thespolytope, it means that data needs to be read or written. An example of... |

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Citation Context ...write MOD terms into DIV terms. There are cases that a DIV term cannot be converted into a MOD term. In such case, we employ modern software compiler techniques to reduce the cost of integer division =-=[1, 9, 10]-=-. These techniques are based on socalled scaled reciprocals. In general, the techniques transform an integer division into a multiplication with a constant and a shifts expressed, see [10]. Also, we c... |