## Expression Synthesis in Process Networks generated by LAURA

Citations: | 1 - 0 self |

### BibTeX

@MISC{Zissulescu_expressionsynthesis,

author = {Claudiu Zissulescu and Bart Kienhuis},

title = {Expression Synthesis in Process Networks generated by LAURA},

year = {}

}

### OpenURL

### Abstract

The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the Expression Compiler that efficiently maps pseudolinear expressions onto a dedicated hardware datapath in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code. 1

### Citations

1046 |
Advanced Compiler Design & Implementation
- Muchnick
- 1997
(Show Context)
Citation Context ...work. This is due to the presence of complex operations such as multiplication and integer division. The elimination of division and modulo operations from a sequential programs has been discussed in =-=[16, 12]-=-. Also the PICO project [15] employs similar techinques to avoid MOD and DIV operations. Our target is to generate a custom datapath implementation, and hence, additional issues have to be taken into ... |

107 | On predicated execution
- Park, Schlansker
- 1991
(Show Context)
Citation Context ... (PSSA) [3] code for a particular target architecture, taking advantage of today’s research in PSSA compilation techniques [3]. The PSSA form is suitable for optimizations either for a microprocessor =-=[14]-=- or for a reconfigurable platform such as FPGA [17] in which we are interested. For an FPGA platform target, the desired operations are: the reduction of the number of variables used, multiplexer opti... |

102 | YAPI: Application Modeling for Signal Processing Systems
- Kock, Essink, et al.
- 2000
(Show Context)
Citation Context ...ion that expresses an application in terms of distributed memory and distributed control. Once the process network is created, the individual processes can either be described in Java [4] or C++ code =-=[5]-=-, or as synthesizable VHDL network of processors suitable for mapping onto FPGAs [20]. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write < 10 ns Figure ... |

64 | PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
- Schreiber, Aditya, et al.
(Show Context)
Citation Context ...e of complex operations such as multiplication and integer division. The elimination of division and modulo operations from a sequential programs has been discussed in [16, 12]. Also the PICO project =-=[15]-=- employs similar techinques to avoid MOD and DIV operations. Our target is to generate a custom datapath implementation, and hence, additional issues have to be taken into account like hardware mappin... |

63 | Deprettere "Compaan: Deriving Process Networks from Matlab for Embedded
- Kienhuis, Rijpkema, et al.
(Show Context)
Citation Context ...flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code. 1 Introduction The aim of the COMPAAN compiler =-=[8, 18]-=- is to automatically derive a parallel description from a nested loop application written in a standard programming language like C or Matlab. The applications COMPAAN targets are compute kernels that... |

53 | System design using Kahn process networks: The Compaan/Laura approach
- STEFANOV, ZISSULESCU, et al.
- 2004
(Show Context)
Citation Context ...dd}@liacs.nl Presented at the 16th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP2005), July 23 – 25, 2005, Samos, Greece Abstract The COMPAAN/LAURA =-=[18]-=- tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a Process Network in which the control is ... |

30 | Predicated Static Single Assignment
- Carter, Simon, et al.
- 1999
(Show Context)
Citation Context ...agation, dead-code elimination, and retiming for gaining the best hardware performance. The Predicated Static Single Assignment Compiler optimizes the input Predicated Static Single Assignment (PSSA) =-=[3]-=- code for a particular target architecture, taking advantage of today’s research in PSSA compilation techniques [3]. The PSSA form is suitable for optimizations either for a microprocessor [14] or for... |

25 |
Passages From the Life of a Philosopher
- Babbage
- 1864
(Show Context)
Citation Context ...his is an important step, as a multiplication takes more FPGA resources and time compared to an addition. The technique that exploits the repetitive behavior is called the Method of Differences (MoD) =-=[2]-=-, as it is based on using differences of the terms of an expression to calculate the next value. Although the method of differences can be applied to a polynomial of any degree, we are dealing only wi... |

24 |
Integer multiplication and division on the HP precision architecture
- Magenheimer, Peters, et al.
- 1988
(Show Context)
Citation Context ...write MOD terms into DIV terms. There are cases that a DIV term cannot be converted into a MOD term. In such case, we employ modern software compiler techniques to reduce the cost of integer division =-=[1, 9, 10]-=-. These techniques are based on socalled scaled reciprocals. In general, the techniques transform an integer division into a multiplication with a constant and a shifts expressed, see [10]. Also, we c... |

21 | LAURA: Leiden Architecture Research and Exploration Tool
- Zissulescu, Stefanov, et al.
(Show Context)
Citation Context ...trol. Once the process network is created, the individual processes can either be described in Java [4] or C++ code [5], or as synthesizable VHDL network of processors suitable for mapping onto FPGAs =-=[20]-=-. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write < 10 ns Figure 1. Running an IP core efficiently in a LAURA Processor KPN synthesis to hardware is d... |

18 |
Attacking the Semantic Gap between Application Programming Languages and Configurable Hardware
- Snider
- 2001
(Show Context)
Citation Context ...re, taking advantage of today’s research in PSSA compilation techniques [3]. The PSSA form is suitable for optimizations either for a microprocessor [14] or for a reconfigurable platform such as FPGA =-=[17]-=- in which we are interested. For an FPGA platform target, the desired operations are: the reduction of the number of variables used, multiplexer optimizations, bit-width, and LUT synthesis for non lin... |

14 | Compilation from matlab to process networks realized in fpga
- Harris, Walke, et al.
- 2001
(Show Context)
Citation Context ...constant divider. 3 Related Work A KPN network generated by COMPAAN may be simulated using software KPN simulators where all expressions that define a polytope are evaluated in a sequential order. In =-=[7]-=-, a similar approach has been tried for a hardware implementation, but for only a very limited set of expressions (no multiplications and pseudo linear operators). To allow for an efficient compilatio... |

14 | Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education - Micheli - 1994 |

13 |
Efficient Static Single Assignment Form for Predication
- STOUTCHININ, FERRIÈRE
- 2001
(Show Context)
Citation Context ...e computation. By extending SSA with predication, every statement in the original computation is tagged with a guard that controls whether or not a statement is actually executed. Advanced techniques =-=[17, 19]-=- can be applied on a PSSA to optimize its output for the FPGA platform. Examples of mid-level optimizations are dead code elimination, constant propagation, and retiming. Examples of low-level optimiz... |

8 |
A fast division technique for constant divisors
- Artzy, Hinds, et al.
- 1976
(Show Context)
Citation Context ...write MOD terms into DIV terms. There are cases that a DIV term cannot be converted into a MOD term. In such case, we employ modern software compiler techniques to reduce the cost of integer division =-=[1, 9, 10]-=-. These techniques are based on socalled scaled reciprocals. In general, the techniques transform an integer division into a multiplication with a constant and a shifts expressed, see [10]. Also, we c... |

8 |
Heterogeneous concurrent modeling and design in java
- Hylands, Kienhuis, et al.
- 2001
(Show Context)
Citation Context ...odel of computation that expresses an application in terms of distributed memory and distributed control. Once the process network is created, the individual processes can either be described in Java =-=[4]-=- or C++ code [5], or as synthesizable VHDL network of processors suitable for mapping onto FPGAs [20]. The T IP =10 ns Worst slack in IP Core Data In Read Execute Write Data Out T Read < 10 ns T Write... |

5 | Modeling and FPGA implementation of applications using parameterized process networks with non-static parameters
- Nikolov, Stefanov, et al.
- 2005
(Show Context)
Citation Context ...ignals in less than this 10 ns. The control program in the Read and Write units is expressed in terms of parameterized polytopes. By evaluating these, we can support parameterized control in hardware =-=[6, 13]-=-. The parameterized polytopes are repeatedly evaluated at run-time. If a particular iteration is within the space defined by thespolytope, it means that data needs to be read or written. An example of... |

2 |
Strength reduction of integer divison and modulo operations
- SHELDON, LEE, et al.
- 2001
(Show Context)
Citation Context ...work. This is due to the presence of complex operations such as multiplication and integer division. The elimination of division and modulo operations from a sequential programs has been discussed in =-=[16, 12]-=-. Also the PICO project [15] employs similar techinques to avoid MOD and DIV operations. Our target is to generate a custom datapath implementation, and hence, additional issues have to be taken into ... |

1 | Deriving efficient control in process networks with compaan/laura
- Derrien, Turjan, et al.
(Show Context)
Citation Context ...ignals in less than this 10 ns. The control program in the Read and Write units is expressed in terms of parameterized polytopes. By evaluating these, we can support parameterized control in hardware =-=[6, 13]-=-. The parameterized polytopes are repeatedly evaluated at run-time. If a particular iteration is within the space defined by thespolytope, it means that data needs to be read or written. An example of... |

1 |
Fast Constan Division Routines
- Li
- 1985
(Show Context)
Citation Context ...write MOD terms into DIV terms. There are cases that a DIV term cannot be converted into a MOD term. In such case, we employ modern software compiler techniques to reduce the cost of integer division =-=[1, 9, 10]-=-. These techniques are based on socalled scaled reciprocals. In general, the techniques transform an integer division into a multiplication with a constant and a shifts expressed, see [10]. Also, we c... |